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Electrical Computers And Digital Data Processing Systems: Input/output > Intrasystem Connection (e.g., Bus And Bus Transaction Processing) > Bus Access Regulation > Centralized Bus Arbitration Centralized Bus ArbitrationCentralized Bus Arbitration patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212632 - On-chip inter-subsystem communication A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an ... 09/07/06 - 20060200608 - Bus arbiter and bus arbitrating method A bus arbiter includes a counter circuit for generating a plurality of output values, wherein each of the output values is generated according to the number of times that one of a plurality of master devices utilizes a bus; and a control circuit for enabling one of the master devices ... 09/07/06 - 20060200607 - Bus access arbitration scheme A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to ... 08/31/06 - 20060195641 - Method and apparatus for assigning bus grant requests Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that ... 08/31/06 - 20060195640 - Memory mapped i/o bus selection A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus ... 08/24/06 - 20060190649 - Plural bus arbitrations per cycle via higher-frequency arbiter An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The ... 08/03/06 - 20060174045 - Bus arbitration method and semiconductor apparatus An access priority in bus arbitration is changed based on a cache hit ratio so as to perform the bus arbitration. In order to perform the bus arbitration, a cache hit ratio measuring device investigates a status of a cache access by a bus master. A bus arbitration managing device ... 07/06/06 - 20060149876 - System and method for implicit transaction control Embodiments of the invention are generally directed to a system and method for implicit transaction control. A transaction manager receives an indication that an operation is to be executed within a transaction. The transaction manager determines whether a preexisting transaction context is available to provide the transaction for the operation. ... 06/29/06 - 20060143349 - Bus arbitration system A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter ... 05/11/06 - 20060101179 - Starvation prevention scheme for a fixed priority pci-express arbiter with grant counters using arbitration pools Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource ... 01/26/06 - 20060020729 - Information processing apparatus and method that utilizes stored information about a mountable device An IEEE 1394-compliant communication bus connects a printer and host computer so as to allow communication. The configuration ROM of the printer stores information about devices mountable on the apparatus. The host computer accesses the configuration ROM via the communication bus to acquire information in a Feature Directory. The Feature ... 01/26/06 - 20060020728 - Bus request control circuit A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request signal to request a bus right to the arbitration circuit. A request acknowledge signal receiving section receives a request acknowledge signal ... 09/29/05 - 20050216632 - Apparatus and method for supporting heterogeneous agents in on-chip busses A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first ... 09/15/05 - 20050204084 - Bus system and method thereof A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the ... 09/08/05 - 20050198420 - Microcomputer minimizing influence of bus contention An edge detecting circuit detects an input level change (edge) of a synchronous signal provided from a synchronous signal input terminal. A data latch unit latches digital data provided from an external data input terminal. An address generating circuit provides an address signal. A write control unit activates/deactivates a write ... 08/25/05 - 20050188138 - Arrangement, device and method for controlling bus request signal generation A device, arrangement and method may control bus request timing to disperse bus access timing, so that adverse effects of concentration-on-bus phenomenon may be avoided. The device may include a bus request signal generating circuit may generate a bus request signal under control of a counter, and a pulse signal ... 08/11/05 - 20050177665 - Method and apparatus of adding grant information to a memory A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical ... 07/28/05 - 20050165988 - Bus communication system A bus communication system for enabling data transfer in synchronized communication is provided, which comprises master circuits, a slave circuit, a bus, and a bus arbitration circuit. Data transfer is performed between the master circuits and the slave circuit via the bus. When a transfer request is output from the ... 07/28/05 - 20050165987 - Systems and methods for bandwidth shaping Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer ... 07/28/05 - 20050165986 - Console chip and one-bus system A one-bus multi-media computer system is provided, including a CPU/Sound/Graphic unit, a bus arbitrator, a program and sound and graphic memory for communicating with CPU/Sound/Graphic unit and the bus arbitrator. Only a single bus is required as communications is through the bus arbitrator. The addition of bus-arbitrator can relieve CPU/Sound/Graphic ... ### FreshPatents.com Support |