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Electrical Computers And Digital Data Processing Systems: Input/output > Intrasystem Connection (e.g., Bus And Bus Transaction Processing) > Bus Access Regulation > Bus Master/slave Controlling Bus Master/slave ControllingBus Master/slave Controlling patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236009 - Data transmitter A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus. ... 10/19/06 - 20060236008 - System and method for removing retired entries from a command buffer using tag information Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master devices and multiple slave devices are coupled to a ... 10/12/06 - 20060230206 - Current mode bus interface system, method of performing a mode transition and mode control signal generator for the same A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference ... 10/12/06 - 20060230205 - Back-off timing mechanism Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static ... 10/05/06 - 20060224804 - Direct memory access for advanced high speed bus A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce ... 10/05/06 - 20060224803 - Mechanism for a shared serial peripheral interface According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between ... 09/21/06 - 20060212631 - Automatic status assignment logic circuit apparatus for bay devices In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third ... 09/07/06 - 20060200606 - Bus connection method and apparatus A system-on-chip (SOC) based on an advanced micro-controller bus architecture (AMBA), and particularly, a bus connection method, is provided. The bus connection method includes: allowing one of a plurality of masters to use a plurality of slaves; generating information necessary for using the slaves by decoding a command generated by ... 09/07/06 - 20060200605 - Electronic apparatus system with master node and slave node An electronic apparatus system is disclosed that comprises at least one (1) master node; and a plurality of slave nodes connected to the at least one (1) master node via an I2C interface, wherein each of the plurality of slave nodes is set to a slave address with an address ... 08/31/06 - 20060195639 - System and method for dynamically allocating inter integrated circuits addresses to multiple slaves A system for dynamically allocating inter integrated circuits (I2C) addresses to multiple slave includes a host (1), a plurality of slaves (2) and an I2C bus (3). Each slave includes a processor (20) for performing an I2C address allocating program (200), which includes a signal setting module (201), a delay ... 08/24/06 - 20060190648 - Secure local network A local network comprises at least one master and a plurality of slaves which can be controlled by the master via a data bus, with at least one slave being arranged in an unprotected region and at least one slave being arranged in n protected region. In this connection, data ... 08/24/06 - 20060190647 - System and method for facilitating communication between devices on a bus using tags Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with a ... 08/10/06 - 20060179193 - Information processor system In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device ... 08/10/06 - 20060179192 - Flow control method to improve bus utilization in a system-on-a-chip integrated circuit A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for ... 08/03/06 - 20060174044 - Multiple master inter integrated circuit bus system A multiple-master Inter Integrated Circuit (“I2C) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. ... 07/27/06 - 20060168380 - Method, system, and storage medium for time and frequency distribution for bufferless crossbar switch systems A bufferless crossbar switch system and technique for synchronization and error recovery between switch line cards is provided. A network switches data through the bufferless data crossbar switch and distributes a high-speed frequency and time signal on a separate channel. The separate channel allows clock recovery, eliminating the need to ... 07/13/06 - 20060155902 - Multi-layer bus system having a bus control circuit A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and connects one of the master connection ports to one of the slave connection ports in response a control signal. The slaves ... 07/06/06 - 20060149875 - Method and system for master devices accessing slave devices Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the master devices and the slave device, wherein the bus controller is configured to receive bus signals from the master ... 07/06/06 - 20060149874 - Method and apparatus of reducing transfer latency in an soc interconnect Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A ... 06/29/06 - 20060143348 - System, method, and apparatus for extended serial peripheral interface A system, method, and apparatus for interchip communication between an extended serial peripheral interface (EPSI) master (210) chip having clocking capability and an EPSI slave (310) chip is disclosed. The method comprises the master chip selecting a slave chip (402), the master clocking data into the slave chip from the ... 06/08/06 - 20060123168 - System and method for dynamically allocating addresses to devices coupled to an integrated circuit bus The present invention provides a system for dynamically allocating addresses to devices (110, 120, 130) coupled to an integrated circuit bus (102). The system includes a master processor (101) and a plurality of slave processors (111, 121, 131) corresponding to the devices. The master processor is used for generating a ... 05/25/06 - 20060112207 - Data transfer apparatus A data transfer apparatus includes at least one master and a plurality of slaves connected by a ring-connection bus, and a controller having a master port and slave ports connected to the corresponding master and slaves, respectively. In such a ring-like structure, a large amount of data can be transferred ... 05/25/06 - 20060112206 - Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given ... 05/25/06 - 20060112205 - Method and apparatus for connecting buses with different clock frequencies A method and an apparatus in a computer system for connecting buses with different clock frequencies are provided. The method comprises receiving a request transmitted from a master to a slave. If the clock frequency of the master is lower than that of the slave such that the slave sees ... 05/18/06 - 20060106963 - Wireless network system and wireless communication program Upon receipt of a network connection request, a CPU core of a game device randomly sets a master device search period, and searches for a master device or a temporary master device until the master device search period ends. When the master device search period ends, the CPU core randomly ... 04/27/06 - 20060090024 - Bus controller A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At least one of slaves I/F 22-0, 22-1, . . . that control slave devices SV0-SV3 upon the request from master devices MS0-MS3 connected to interconnection bus BS ... 04/13/06 - 20060080485 - Bus system and semiconductor integrated circuit A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information ... 04/06/06 - 20060075170 - System and method for high voltage bidirectional communications interface A system and method for providing an interface between a master device referenced at a first voltage and a slave device referenced at a second voltage. The system includes a bidirectional communications link between the master device and the slave device and a bidirectional transceiver device in the communications link ... 04/06/06 - 20060075169 - Bus deadlock avoidance Bus logic, a data processing apparatus and a method is disclosed. The bus logic is operable to couple a plurality of master logic units with a plurality of slave logic units to enable data transfers to occur, each master logic unit being operable to perform an address transfer which, when ... 03/30/06 - 20060069832 - Information processing apparatus and method and program An information processing apparatus including a plurality of slave processors connected to a system bus and a main processor controlling the plurality of slave processors includes holding means for holding profile information of processing modules executable by the slave processors, selection means for selecting processing modules to be executed by ... 02/09/06 - 20060031614 - Bus switch circuit and bus switch system A bus switch circuit having plural master side interface circuits inputting/outputting signals for plural bus masters respectively, and one or plural slave side interface circuit(s) inputting/outputting signals for one or plural bus slave(s), is provided. The master side interface circuit and the slave side interface circuit input an interrupt signal ... 01/05/06 - 20060004938 - Communication apparatus including dual timer units A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of ... 12/29/05 - 20050289269 - Slave device, master device and stacked device A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit ... 12/29/05 - 20050289268 - Internal bus system A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses ... 12/08/05 - 20050273539 - Data transfer method and data transfer device A data transfer method which is capable of transferring a predetermined amount of data in one transaction at only one time, and preventing the number of ports of a master chip and the number of signal lines connected between the master chip and slave chips from being increased. A single ... 12/08/05 - 20050273538 - Data processor A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting ... 12/08/05 - 20050273537 - Write response signalling within a communication bus An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read ... 12/08/05 - 20050273536 - Handling of write transactions in a data processing apparatus A data processing apparatus and method of handling write transactions in such an apparatus is provided. The apparatus has a plurality of devices, and bus circuitry providing connection paths between the plurality of devices. At least one of the devices has a bus master interface operable to generate write transactions ... 12/08/05 - 20050273535 - Write transaction interleaving A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be ... 12/01/05 - 20050268012 - Method for automatic configuration of a process control system and corresponding process control system According to the invention a method for automatic configuration of a process control system is provided, comprising a master and at least one slave, wherein the master controls the at least one slave, which is connected to and communicates with the master via a bus system, and processes data received ... 12/01/05 - 20050268011 - Method, protocol and system for bidirectional communication in a communication system Described is a method for data communication in a communication system. The system includes a plurality of communication participants, each participant having a subsystem responsible for communication. A communication participant acts as master of the communication system, the subsystem of the master being operated continuously. The other communication participants act ... 11/17/05 - 20050256987 - Method for implementing resets in two computers A method and computer program for implementing a reset both in a master computer and a slave computer which are both connected to a shared data bus. To allow a different reset configuration of both computers even when the slave computer, in particular, has no possibility of an internal slave-reset ... 11/17/05 - 20050256986 - Slave devices and methods for operating the same A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock ... 11/10/05 - 20050251603 - Time setting system and time setting method The present invention provides a time setting system and method thereof that are capable of correctly setting time if a delay occurs in the transmission of time information. In the system for setting a master time outputted from a master apparatus to a slave time of a slave apparatus that ... 10/27/05 - 20050240697 - Enhanced structure of extensible time-sharing bus An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination of two control lines to determine address transfer, data read ... 10/20/05 - 20050235084 - Bus system and access control method The bus system includes a plurality of masters, a plurality of slaves, and a multilayer switch. The bus system further includes an access control register to which access control information is set by a predetermined secure master. The multilayer switch includes switch master portions and switch slave portions. When a ... 10/13/05 - 20050228915 - Pipelined stop, start, address byte, and data byte technique and circuit for i2c logic system Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in response to the stop bit to automatically send a ... 10/13/05 - 20050228914 - Matrix type bus connection system A matrix type bus connection system has a plurality of master devices and a plurality of slave devices. Each slave device has an arbitration circuit. The arbitration circuit stores an address of a master device that made the access the last time, and continues holding a select signal to a ... 10/13/05 - 20050228913 - Communication apparatus implementing time domain isolation with restricted bus access A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests ... 10/06/05 - 20050223147 - Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights in a multimaster bus system (2), having the following steps: addresses (MASTER0-MASTER 15) are explicitly allocated to master devices (3-1, . . . 3-N) in the multimaster bus system, a priority value (P0, . . . P15) from an organized priority list (5) ... 09/29/05 - 20050216631 - Serial digital communication system and method A communication system includes a master device which communicates with a chain of serially-connected slave devices. The master originates messages, each of which is intended for a particular ‘target’ slave device. Each message contains a ‘distance to target device’ value equal to the number of devices between the master and ... 09/08/05 - 20050198419 - Data transfer memory A data transfer memory for reducing the number of components in an electronic module. A master controller circuit provides a transfer start command to a master clock signal generator circuit when receiving an activation detection signal from a power activation detection circuit. As a result, the master clock signal generator ... 08/25/05 - 20050188137 - Matrix type bus connection system and power reduction method therefor A matrix type bus connection system comprising a plurality of master devices and slave devices, wherein data transfer between arbitrary master device and slave device is available, and the power reduction method therefor is disclosed. When a slave device is to be setting to low-power operation state, decoding table contents ... 08/11/05 - 20050177664 - Bus system and method thereof A bus system including first and second blocks. The bus system is configured such that data may be transferred at the first block at the same time that data may be transferred at the second block. ... 08/11/05 - 20050177663 - Method of using bus and bus interface A method of using a bus, includes: determining whether a subject unit among a plurality of units corresponding to masters obtaining a bus use permission from an arbiter uses the bus as a master to transfer data to/from a first unit corresponding to a slave; and converting the first unit ... 08/04/05 - 20050172059 - Data communication system and controller A data communication system uses an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices. The system includes a master device connected to a plurality of slave devices via a data transmission bus by which the master device transfers data ... 06/23/05 - 20050138253 - Advanced microcontroller bus architecture (amba) system with reduced power consumption and method of driving amba system In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can ... 06/23/05 - 20050138252 - Transaction request servicing mechanism A data processing apparatus comprises a master device 150, 160, 170, 180, a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a ... 06/16/05 - 20050132113 - Method for configuring and/or operating an automation device A method and an engineering system, which reduce the extent of configuration work with regard to a possible expansion of the automation device. A configured automation device can thus be expanded during the control of the automation device by means of slave modules. During a configuration phase, the number of ... 06/16/05 - 20050132112 - I/o energy reduction using previous bus state and i/o inversion bit for bus inversion A bus inversion method and system for capturing a previous state of a bus and its corresponding inversion bit prior to transmitting new information over the bus. The new information, state of the bus and associated inversion bit are used to determine whether the new information should be inverted before ... ### FreshPatents.com Support |