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Electrical Computers And Digital Data Processing Systems: Input/output > Intrasystem Connection (e.g., Bus And Bus Transaction Processing) > Bus Access Regulation Bus Access RegulationBus Access Regulation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236007 - Apparatus to improve bandwidth for circuits having multiple memory controllers An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal ... 09/28/06 - 20060218327 - Information handling system including detection of an audio input device An information handling system (“IHS”) including a processor is provided. The IHS also includes an audio input device interface coupled to the processor. Moreover, the IHS includes a voltage regulator coupled to the interface for determining whether an audio input device is coupled to the interface. The voltage regulator also ... 08/10/06 - 20060179191 - Covert channel firewall A method and apparatus for restricting an access operation on a bus cycle to a particular address range. The method may include receiving, by a controller hub, a cycle's address from a device and comparing the address against a valid address list stored in the controller hub to determine if ... 07/27/06 - 20060168379 - Method, system, and apparatus for link latency management A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately ... 06/22/06 - 20060136634 - Data address security device and method Methods and devices for monitoring transactions on a bus are disclosed herein. An embodiment of the device comprises a memory component and a comparator component. The memory component stores at least one address. The comparator component is operatively connected to the memory component and the bus. The comparator component compares ... 06/15/06 - 20060129727 - Dual layer bus architecture for system-on-a-chip A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary memory operating independently of the main bus and adapted to ... 06/15/06 - 20060129726 - Methods and apparatus for processing a command In a first aspect, a first method is provided for processing commands on a bus. The first method includes the steps of (1) in a first phase of bus command processing, receiving a new command from a processor in a memory controller via the bus, wherein a command on the ... 06/15/06 - 20060129725 - Round-robin bus protocol The invention provides a low-latency, peer-to-peer TDM bus and bus protocol in which multiple devices may communicate without the presence of a bus master controller. The bus comprises one or more data lines and one or more control lines. Each device is assigned a unique binary address, and the devices ... 05/04/06 - 20060095622 - System and method for improved memory performance in a mobile device A system and method are disclosed for improved memory performance in a mobile device. A mobile device incorporating teachings disclosed herein may include, for example, a central processing unit (CPU) residing on a first chip. The mobile device may also include a memory system residing on a second chip. The ... 04/27/06 - 20060090023 - Computer and method for on-demand network access control A computer and method that control access to a network. The computer includes an application that shrinks the window of opportunity for a network attack and reduces power consumption by automatically causing a computer to connect to the network when access is needed and to disconnect the computer from the ... 03/30/06 - 20060069831 - I2c bus controlling method A module has an IC for communication control (a PHY unit) and an EEPROM (or MCU) connected to the PHY unit via an I2C bus. When a software reset is triggered while the PHY unit reads non-volatile register (NVR) data from the EEPROM (or MCU) via the I2C bus, the ... 03/30/06 - 20060069830 - Data processing system with bus access retraction A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence ... 03/16/06 - 20060059283 - Method for operating a field device for automation technology In a method for operating an automation technology field device connected via a bus system with a superordinated unit and having an identifier identifying the type of the field device, at least one alternative identifier AKF1, which identifies a similar type of field device, is stored, in addition to an ... 02/23/06 - 20060041700 - System controller, control system, and system control method The present invention is carried out to provide a system controller, a control system and a system control method which are inexpensive, highly stable, capable of storing all information and past record at a time when one of the devices is down and capable of switching the devices without any ... 01/19/06 - 20060015667 - Combined command and response on-chip data interface An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second ... 12/29/05 - 20050289267 - Linking addressable shadow port and protocol for serial bus networks Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol ... 12/08/05 - 20050273534 - High speed peripheral interconnect apparatus, method and system A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory ... 10/13/05 - 20050228912 - Memory address bus termination control A memory device includes address bus termination circuitry that can be enabled or disabled depending on the state of an address bus termination control signal. A memory module may be made up of several of these memory devices with each memory device including address bus termination circuitry. The memory devices ... 09/08/05 - 20050198418 - Multilayer system and clock control method The multilayer system of this invention is characterized by the process when a first master such as a CPU to which a clock signal is constantly supplied from a clock generator activates a second master. First, the first master outputs an activation signal for activating the second master to the ... 07/28/05 - 20050165985 - Network protocol processor Disclosed are techniques for processing a packet. A packet is received. Context data for the packet is located in a storage area. The packet is processed using the context data. Also disclosed is a network protocol processor with an interface to receive a packet, a cache to store context data ... 06/23/05 - 20050138251 - Arbitration of asynchronous and isochronous requests Machine-readable media, methods, and apparatus are described to arbitrate between asynchronous requests and isochronous requests. In one embodiment, an arbiter defines a service period comprising an asynchronous portion followed by an isochronous portion. During the asynchronous portion, the arbiter first services asynchronous requests and then services isochronous requests if no ... ### FreshPatents.com Support |