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Electrical Computers And Digital Data Processing Systems: Input/output > Input/output Data Processing > Input/output Process Timing Input/output Process TimingInput/output Process Timing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218318 - Method and system for synchronizing communications links in a hub-based memory system A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller. The method includes synchronizing each upstream and ... 09/28/06 - 20060218317 - Systems and methods for driving data over a bus Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed ... 09/21/06 - 20060212618 - Device for exchanging data signals between two clock domains A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of ... 09/07/06 - 20060200598 - System and method for optimizing interconnections of components in a multichip memory module An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, ... 07/20/06 - 20060161699 - Identifying a processor in a multiprocessor system A method for storing an identity of a processor in a multiprocessor computer system, the processor including a high frequency clock having a clock value represented as a set of binary digits, the method comprising encoding an identifier of the processor in a subset of the set of binary digits. ... 07/06/06 - 20060149867 - Bus system design method, bus system, and device unit On the basis of a period of a timing signal, a signal propagation delay in a device unit, signal propagation delay in the timing signal bus and the data bus, and a setup time of another device unit or a device connected to the data bus, a timing at which ... 06/29/06 - 20060143337 - Display controller A display controller including: a host I/F which performs interface processing between the display controller and a host CPU; a memory into which a multimedia processing program is loaded, when the host CPU has read the multimedia processing program from a multimedia processing program group stored in a host memory ... 06/29/06 - 20060143336 - System and method for synchronous processing of media data on an asynchronous processor The present invention provides a method and system for processing media data on a host processor. The method and system involve receiving media data, generating clocking signals, transferring media data to host processor buffers, generating media transfer done interrupts for each media data stream and generating an override interrupt to ... 06/29/06 - 20060143335 - System for transmission of synchronous video with compression through channels with varying transmission delay The present invention overcomes limitations of conventional synchronous signal transmission systems. The present invention provides apparent low latency synchronous signal transmission between devices, even if the transmission channel has impairments, and, allows for asynchronous transmission of signals between a transmitters and receivers that are located between the devices. Compression is ... 06/22/06 - 20060136620 - Data transfer interface apparatus and method thereof A data transfer interface apparatus and method for controlling data transfer. The data transfer interface apparatus includes a first storage unit for storing an input data according to a first clock and for outputting a first output data according to a second clock, a single-port memory coupled to the first ... 06/15/06 - 20060129720 - Data buffer circuit, interface circuit and control method therefor There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in ... 06/15/06 - 20060129719 - System and method for ordering haptic effects A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on ... 06/08/06 - 20060123163 - Communication control circuit and communication control method A communication control circuit that performs the process of receiving a response to send data in synchronous transfer mode within a certain period of time without using an external control circuit. A permissible time calculation section calculates permissible time for receiving response data corresponding to send data sent to each ... 06/08/06 - 20060123162 - Multimodal data switch A transit memory assembly of a rotator-based switching node is logically partitioned into two sections, one operated as a common-memory switch fabric and the other as a time-shared space-switch fabric. The composition of data received at input ports of the switching node determines adaptive capacity division between the two sections. ... 05/11/06 - 20060101173 - Pin sharing system The present invention discloses a pin sharing system for sharing with a peripheral device one of a plurality of pins configured between an ATA device and an I/O device. The system includes a peripheral controller, an ATA controller, and an I/O controller. The peripheral controller is used for receiving a ... 04/27/06 - 20060090019 - Asynchronous communications technique A main processor manages serial communication with one or more external devices by establishing the requisite tasks needed for serial communications. For example, these tasks can include (1) serial device handling, (2) protocol encapsulation, and (3) low-level communication with external devices. A priority is assigned to each of the tasks ... 04/06/06 - 20060075165 - Method and system for processing out of order frames A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the ... 04/06/06 - 20060075164 - Method and apparatus for using advanced host controller interface to transfer data A method and apparatus for entering a mode of a host controller and omitting a state of a state machine sequence of the host controller for data exchange by the host controller are disclosed. For one embodiment, the method and apparatus include setting a bit before a command information is ... 03/16/06 - 20060059280 - Digital programming interface between a baseband processor and an integrated radio-frequency module A circuit receives a clock signal, a data word which is emitted from a control device and has information about a read or write access to the circuit, and an enable signal which is at a predetermined value during the transmission of the data word. A determination unit uses the ... 02/23/06 - 20060041693 - Asynchronous decoupler A decoupler that allows for asynchronous communication between two synchronous IP cores. The decoupler reduces or eliminates the need for distribution and balancing of the clock. More specifically, the decoupler provides the ability to decouple an IP core from the interconnect clock domain, thereby reducing the need for clock balancing. ... 02/16/06 - 20060036783 - Method and apparatus for content presentation The invention relates to a system for content presentation of content signals such as video signals. A content presentation apparatus comprises a content signal receiver (201) receiving a content signal from a content source (203). The signal is stored in a memory (205). The memory is connected to a content ... 02/02/06 - 20060026314 - Communication controller with automatic time stamping Devices in a process control system communicate by data messages over a communication medium segment. Each device includes a communication controller that automatically time stamps events associated with received and transmitted messages. ... 12/08/05 - 20050273529 - Fencing of resources allocated to non-cooperative client computers Techniques are provided for processing an Input/Output (I/O) request. At least one data block is allocated for use in completing the I/O request. A current operations record is stored for the I/O request. It is determined whether the I/0 request has been completed within a specified period of time. In ... ### FreshPatents.com Support |