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Electrical Computers And Digital Data Processing Systems: Input/output > Input/output Data Processing > Direct Memory Accessing (dma) Direct Memory Accessing (dma)Direct Memory Accessing (dma) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236001 - Direct memory access controller a transfer control unit issues commands that the transfer data is divided into portions each having a prescribed transfer unit size. The portions of transfer data are sent separately to the device associated with the transfer destination address in such a manner that the final portion of the data to ... 10/19/06 - 20060236000 - Method and system of split-streaming direct memory access A method and system of split-streaming direct memory access (DMA) data transfer can transfer N words of data from a source device to two different sets of memory locations using only N data read cycles and 2N data write cycles. In a single data word transfer mode, a data read ... 09/28/06 - 20060218313 - Dma circuit and computer system A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state ... 09/14/06 - 20060206635 - Dma engine for protocol processing A DMA engine, includes, in part, a DMA controller, an associative memory buffer, a request FIFO accepting data transfer requests from a programmable engine, such as a CPU, and a response FIFO that returns the completion status of the transfer requests to the CPU. Each request includes, in part, a ... 09/14/06 - 20060206634 - Dma controller A DMA controller is connected by a bus to a plurality of master devices and a plurality of slave devices, and performs a data transfer between slave devices which are specified as a source and a destination of the data transfer by a transfer condition received from any of the ... 09/14/06 - 20060206633 - System and method for dma transfer A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to ... 08/31/06 - 20060195628 - System and method for dma transfer between fifos A system for DMA transfer includes a CPU core having a DMA function, a first macro including a FIFO having a first bit width, and a second macro including a FIFO having a second bit width narrower than the first bit width, wherein an address signal fixing circuit is provided, ... 08/24/06 - 20060190637 - Control apparatus, information processing apparatus, and data transferring method A control apparatus has a memory, a processor, an input/output controller, and an interrupt controller. The processor is accessible to the memory. The input/output controller starts to transfer data from an input/output device to write the data to a given area in the memory not through the processor, reads data ... 08/24/06 - 20060190636 - Method and apparatus for invalidating cache lines during direct memory access (dma) write operations A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not ... 08/10/06 - 20060179181 - Apparatus and method for controlling direct memory access Provided is an apparatus and method for controlling a Direct Memory Access (DMA). The apparatus includes a plurality of control registers and a control register selection module. The sequentially selects one of the plurality of control registers according to a predetermined change point and a previously stored control register change ... 08/10/06 - 20060179180 - Signal processing apparatus, signal processing system and signal processing method An apparatus includes a first direct memory access controller which successively processes first descriptors, thereby executing a series of data transfers for reading first data, which is stored in a memory, and generates an activation signal in a case where a current to-be-processed first descriptor of the first descriptors includes ... 08/10/06 - 20060179179 - Methods and apparatus for hybrid dma queue and dma table Methods and apparatus provide for assigning an identifier to a DMA command, the identifier for association with an entry of a DMA table containing status information regarding the DMA command; receiving an indication that a DMA data transfer defined by the DMA command has been completed; and updating the status ... 08/10/06 - 20060179178 - Techniques to manage data transfer Techniques to indicate whether datum transferred from a memory device to a second device is likely to be accessed again by the second device. The second device may include a buffer memory to store the datum when the datum is indicated as likely to be accessed again. If the second ... 08/10/06 - 20060179177 - Method, apparatus, and computer program product for migrating data pages by disabling selected dma operations in a physical i/o adapter A method, apparatus, and computer program product are disclosed in a data processing system for migrating data pages subject to DMA access by temporarily disabling selected DMA operations within a physical I/O adapter. A determination is made as to whether to disable data access DMA capabilities of the physical I/O ... 08/10/06 - 20060179176 - System and method for a memory with combined line and word access A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a ... 08/10/06 - 20060179175 - Method and system for cache utilization by limiting prefetch requests System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a number of pending memory requests for the entity is less than a prefetch limit therefor; and responsive to a ... 08/10/06 - 20060179174 - Method and system for preventing cache lines from being flushed until data stored therein is used System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and responsive to a determination that ... 08/10/06 - 20060179173 - Method and system for cache utilization by prefetching for multiple dma reads System and method of memory utilization in a computer system are described. In one embodiment, the method comprises storing a DMA transaction received from an entity in a request address first-in, first out buffer (“RAF”); determining whether a first DMA transaction stored in the RAF is a read request; and ... 08/10/06 - 20060179172 - Method and system for reducing power consumption of a direct memory access controller A method and system for reducing the power consumption of a direct memory access (DMA) controller. A preferred method, for example, comprises: queuing a first DMA request in a queue; responding to the first queued DMA request when the computer system resources necessary for a DMA transfer are available; and ... 07/27/06 - 20060168368 - Method for updating firmware in the control chip A control chip for updating firmware in an optical disk drive by hardware. The control chip includes a microprocessor for controlling actions of the optical disk drive, a decoder controlled by the microprocessor and connected to an external buffer memory and a host interface, a controller controlled by the microprocessor ... 07/27/06 - 20060168367 - Integrated circuit having multiple modes of operation A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include first circuitry and second circuitry. The first circuitry may be capable of performing at least one operation including, at least in part, generating check data based at ... 07/27/06 - 20060168366 - Direct memory access control method, direct memory access controller, information processing system, and program In a DMA control method in which a DMA controller transfers data in memory to an input/output device in accordance with the control information which is provided by a processing device to a DMA controller, a processing device implements a step in which the processing device sets an information block ... 07/27/06 - 20060168365 - Method for programming a dma controller in a system on a chip and associated system on a chip A method is provided for programming a DMA controller in a system on a chip. According to the method, a memory management unit translates a programming virtual address into a programming physical address according to a translation table. A first sub-block without discontinuity beginning at the programming physical address and ... 07/20/06 - 20060161696 - Stream processor and information processing apparatus An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be ... 07/20/06 - 20060161695 - Direct memory access system A direct memory access system has a DMA setting decoding portion 17 and a DMA clock/reset control portion 18. The DMA setting decoding portion 17 acquires various pieces of DMA data transfer control information including a data transfer length and a data transfer target from information set in a DMA ... 07/20/06 - 20060161694 - Dma apparatus A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from ... 07/06/06 - 20060149862 - Dma in processor pipeline The present technique is an atomic technique that places a triggered operation within a processor pipeline, whereby the processor is stalled until the triggered operation is completed. A processor issues an access operation that will trigger an external block operation. The external operation does not return an access valid until ... 07/06/06 - 20060149861 - Methods and apparatus for list transfers using dma transfers in a multi-processor system Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the ... 06/29/06 - 20060143329 - Direct memory access circuit and disk array device using same A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the descriptor, in a predetermined part of the descriptor, and stores the descriptor in memory, and when a ... 06/22/06 - 20060136613 - Duplicate synchronization system and method of operating duplicate synchronization system The duplicate synchronization system has: a first system; and a second system operating in synchronization with the first system. The first and the second systems are connected to each other. The first system includes: a first memory; a first memory controller; and a first DMA engine. The second system includes: ... 06/22/06 - 20060136612 - System and method for passing information from one device driver to another A system and method for passing Direct Memory Access (DMA) configuration information from one device driver to another in order to initialize devices for DMA operations are provided. More specifically, a mechanism for passing information, identifying a DMA address space allocated to a child virtual device, from the child virtual ... 06/22/06 - 20060136611 - Chipset feature detection and configuration by an i/o device Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code ... 06/15/06 - 20060129708 - Information processing apparatus and method and recording medium A control machine which uses a data amount stored in a FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for ... 06/15/06 - 20060129707 - Data transfer apparatus and data transfer method A data transfer apparatus receives comparison data to be compared with stored data from an external unit, searches data corresponding to the comparison data from among the stored data, and transfers the searched data to the external unit. A control unit generates comparison-condition information for searching predetermined stored data from ... 06/15/06 - 20060129706 - Telecommunication network and upgrading method therefore For upgrading a section of a telecommunication network comprising two nodes, one of the data lines interconnecting the nodes is selected to be a carrier of redundant specimens of information units to be transmitted. An external condition is fulfilled, which is detected by a control unit of the node and ... 06/08/06 - 20060123153 - Method and system for testing remote i/o functionality A method and system for testing a remote I/O sub-assembly. The method including: allocating source memory, destination memory and DMA queue memory location in a memory of the remote I/O sub-assembly; writing a pattern of test data into the source memory location; writing a set of descriptors simulating data transfer ... 06/08/06 - 20060123152 - Inter-processor communication system for communication between processors System comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via two bi-directional communication channels for exchanging information. For establishing the bi-directional communication channels, the system comprises a first processor bus (10) to which the first processor (P1) is connected, a ... 06/01/06 - 20060117119 - Enhanced power reduction capabilities for streaming direct memory access engine A streaming direct memory access (DMA) engine is disclosed. The streaming DMA engine includes several power reduction capabilities. A controller throttles the DMA engine according to the system throughput requirement and the system processor operation state. The DMA engine holds off a new read request to the memory if the ... 05/25/06 - 20060112199 - Method and system for dma optimization in host bus adapters Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a certain write burst size to adjust ... 05/11/06 - 20060101166 - Method and system for structured dma transactions Disclosed is a structured model for developing DMA code and for performing DMA transactions. This model of structured DMA transactions provides a framework with default behaviors. Developers need only provide a minimal amount of configuration information and can then characterize subsequent DMA transactions in terms of a profile, thus reducing ... 05/11/06 - 20060101165 - Device including means for transferring information indicating wether or not the device supports dma A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access. ... 05/04/06 - 20060095604 - Implementing bufferless dma controllers using split transactions According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller ... 04/27/06 - 20060090017 - Microprocessor system with memory device including a dmac, and a bus for dma transfer of data between memory devices A processor system having a memory device including a (RAM) memory and a direct memory access controller (DMAC) and an internal bus switchably connected between the memory and the DMAC. A Bus Switch (multiplexer) within the memory device alternately establishes a first data transmission path over the system bus between ... 04/27/06 - 20060090016 - Mechanism to pull data into a processor cache A computer system is disclosed. The computer system includes a host memory, an external bus coupled to the host memory and a processor coupled to the external bus. The processor includes a first central processing unit (CPU), an internal bus coupled to the CPU and a direct memory access (DMA) ... 04/27/06 - 20060090015 - Pipelined circuit for tag availability with multi-threaded direct memory access (dma) activity A method and system for determining multi-thread direct memory activity is described. A pipelined circuit for tag availability with multi-threaded direct memory access activity may be employed. The pipelined circuit includes registers for providing a tag to a direct memory access (DMA) thread and receiving the tag upon completion of ... 04/20/06 - 20060085570 - Disk controller and storage system A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and ... 04/20/06 - 20060085569 - Method for minimizing the translation overhead for large i/o transfers A number of DMA addresses are resolved to system memory addresses at a time to decrease latency time. The number of addresses resolved at a time is preferably correlated to the number of DMA addresses that can be stored in a single cache line. Additionally, system memory is allocated in ... 04/13/06 - 20060080479 - Information processing apparatus A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A stream processor for performing a plurality of processes parallel to ... 04/13/06 - 20060080478 - Multi-threaded dma A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and ... 04/13/06 - 20060080477 - Multi-channel dma with shared fifo A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) ... 04/06/06 - 20060075158 - Information processing apparatus and data transfer control method An I/O controller to which an I/O device is connected includes a DMA controller (DMAC) and an access control unit (ACU). The DMAC executes DMA transfer in accordance with data transfer control information set in a control/status register by a user process. The ACU limits execution of DMA transfer by ... 04/06/06 - 20060075157 - Programmable memory interfacing device for use in active memory management An interface device for manipulating the data inside a memory or for assisting in manipulating the data between the memory and a nearby processor is disclosed. The device is a programmable core, having a limited instruction set designed for data layout transformations, pointer-chasing and data congregation/distribution. It is attached to ... 03/30/06 - 20060069818 - Synchronizing direct memory access and evacuation operations in a computer system A computer-implemented method for performing an evacuation request pertaining to a set of memory pages. The method includes inhibiting new DMA operations on a range of memory, the range of memory overlaps with at least a first portion of the set of memory pages associated with the evacuation request. The ... 03/23/06 - 20060064518 - Method and system for managing cache injection in a multiprocessor system A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of ... 03/23/06 - 20060064517 - Event-driven dma controller A DMA memory controller includes a program module operable to receive and execute instructions comprising instructions to perform multiple DMA transfers. The multiple DMA transfers are triggered by a hardware event. A hardware event monitor is operable to detect hardware events and to report the detected hardware events to the ... 03/23/06 - 20060064516 - Instruction removal for context re-evaluation A mechanism is provided for removal of instructions for context re-evaluation. The mechanism receives an external request to perform the instruction remove. In response to this external request, the mechanism next determines when the state of the system is stable for allowing the instruction remove. Then the mechanism creates a ... 03/09/06 - 20060053236 - Method and system for optimizing dma channel selection A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection ... 03/02/06 - 20060047866 - Computer system having direct memory access controller A computer system which includes a DMAC that can control a transfer rate when data is transferred within a memory. The computer system is provided with a variable pulse generation unit, connected to a system bus, for generating a pulse signal having a period and a pulse width that are ... 03/02/06 - 20060047865 - Skip mask table automated context generation Skip logic is provided in a storage controller that informs a direct memory access (DMA) context list manager of consecutive ones and zeroes in a skip mask table. The DMA context list manager then manages data counters and location pointers based on the number of consecutive ones and the number ... 03/02/06 - 20060047864 - System and method for dma controller with multi-dimensional line-walking functionality A system and method for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves through a memory map and retrieves data based upon the line description ... 02/09/06 - 20060031604 - Dma transfer apparatus and method of controlling data transfer A direct-memory-access transfer apparatus includes an information reading unit that reads transfer-count information from a memory before starting data transfer prior to transferring data stored in the memory; a data transferring unit that transfers the data stored in the memory; and a transfer controlling unit that controls, when the information ... 02/09/06 - 20060031603 - Multi-threaded/multi-issue dma engine data transfer system A multi-threaded DMA engine data transfer system for a data processing system and a method for transferring data in a data processing system. The DMA Engine data transfer system has at least one frame buffer for storing data transmitted or received over an interface. A multi-threaded DMA engine generates a ... 02/09/06 - 20060031602 - Scalable architecture for context execution System, apparatus and method for controlling the movement of data in a data processing system. The apparatus receives commands from at least one protocol engine and generates contexts representing the commands. The contexts are a data structure representing information for programming data transfers pursuant to the commands. Instruction requests based ... 02/09/06 - 20060031601 - Apparatus and method to convert data payloads from a first sector format to a second sector format The method forms a plurality of DMA data payloads each comprising a plurality of first sectors, and sends to a sector format conversion device one or more of those DMA data payloads. The method then overlays the (i)th DMA data payload onto part or all of a plurality of second ... 02/09/06 - 20060031600 - Method of processing a context for execution The present invention is a method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes a buffer for storing data transferred in response to execution of a direct memory access ... 02/02/06 - 20060026311 - Procedure for programming a dma controller in a system on a chip and associated system on a chip A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address ... 02/02/06 - 20060026310 - Computer system having an i/o module directly connected to a main storage for dma transfer A computer system includes a CPU (Central Processing Unit) and a main storage interconnected by a bus to the CPU. The I/O module for transferring received data and data to be transmitted to and from an external unit is directly connected to the main storage, which stores the received data ... 02/02/06 - 20060026309 - Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the ... 02/02/06 - 20060026308 - Dmac issue mechanism via streaming id method An apparatus, a method and a computer program are provided for executing Direct Memory Access (DMA) commands. A physical queue is divided into a number of virtual queues by software based on the command type, such as processor to processor, processor to Input/Output (I/O) devices, and processor to external or ... 02/02/06 - 20060026307 - Method for direct memory access, related architecture and computer program product A method of exchanging data within a direct memory access (DMA) arrangement including a plurality of IP blocks (A, B, C) includes the step of associating with the IP blocks (A, B, C) respective DMA modules (IDMA A. IDMA B, IDMA C) each DMA module including an input buffer (11A, ... 01/26/06 - 20060020719 - Procedure for programming a dma controller in a system on a chip and associated system on a chip A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the ... 01/12/06 - 20060010263 - Direct memory access (dma) devices, data transfer systems including dma devices and methods of performing data transfer operations using the same Data transfer systems are provided. The data transfer systems include a bridge direct memory access (DMA) device. A first memory is electrically coupled to the bridge DMA device and a second memory is electrically coupled to the bridge DMA device. The bridge DMA device is configured to control data transfer ... 01/12/06 - 20060010262 - Procedure for processing a virtual address for programming a dma controller and associated system on a chip A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is ... 01/12/06 - 20060010261 - Highly concurrent dma controller with programmable dma channels A data transaction controller for transferring data responsive to a request from a client. The data transaction controller includes channel circuitry for providing a channel for data transfers. The channel circuitry includes a first storage device for storing channel configuration data. The data transaction controller further includes control circuitry for ... 01/12/06 - 20060010260 - Direct memory access (dma) controller and bus structure in a master/slave system Direct memory access (DMA) controllers of a master/slave computer system and methods for transferring data under a DMA protocol in a master/slave system are disclosed herein. A DMA controller according to the present application comprising a first data path connected to a memory bus, wherein the memory bus is in ... 01/05/06 - 20060004932 - Multi-directional data transfer using a single dma channel A single direct memory access (DMA) channel provides bi-directional transfer of data between two devices by selectively swapping the source and destination registers of the DMA channel in response to a binary control signal. The source of the control signal can be one of the devices involved in the data ... 01/05/06 - 20060004931 - Memory access bandwidth allocation and latency control in a digital camera Memory access bandwidth within a digital camera is allocated among several requestors by assigning each requester a “tokens per snapshot” (TPS) value. Each requestor has a DMA engine and a DMA entry queue. If the requester wishes to access the memory, then a DMA entry is pushed onto the DMA ... 12/29/05 - 20050289253 - Apparatus and method for a multi-function direct memory access core A method and apparatus for a multi-function direct memory access core are described. In one embodiment, the method includes the reading of a direct memory access (DMA) descriptor having associated DMA data to identify at least one micro-command. Once the micro-command is identified, the DMA data is processed according to ... 11/24/05 - 20050262276 - Design method for implementing high memory algorithm on low internal memory processor using a direct memory access (dma) engine A design method for implementing a high-memory algorithm for motion estimation and compensation uses a low internal memory processor and a DMA engine that interacts with the processor and the algorithm. The DMA takes care of large data transfers from an external memory to the processor internal memory and vice-versa, ... 11/24/05 - 20050262275 - Method and apparatus for accessing a multi ordered memory array A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a ... 11/17/05 - 20050256979 - [direct memory access method for card reader and a method for programming controller of card reader] A direct memory access method for A card reader and a method for programming A controller of the card reader are provided. This method actively sets the DMAC and uses the table established by the block status recording area of the memory card to set the DMAC parameter set. The ... 10/27/05 - 20050240688 - Efficient data transfer from an asic to a host using dma A method comprising generating a transfer configuration descriptor (“TCD”), said TCD comprising information pertaining to data to be transferred. The method further comprises dynamically configuring a direct memory access (“DMA”) channel based on said TCD without using a CPU and transferring a group of data blocks by way of said ... 10/20/05 - 20050235072 - Data storage controller Tags are associated with commands in a data storage system. Through the use of these tags, routing and processing of commands and data associated with the commands may be handled by software and/or one or more hardware ports. As a result data processing and routing may be automated and wide-ports ... 10/06/05 - 20050223137 - Dual ide channel servicing using single multiplexed interface An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For multiple channel transfers to hard disk drive storage, a multiplexed IDE host interface is provided with shared pins for data, address, and chip-select lines of the IDE interface ... 10/06/05 - 20050223136 - System and method for controlling dma data transfer A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored ... 10/06/05 - 20050223135 - Data transfer processing device and data transfer processing method A transfer request processing portion 10 confirms the kind of requested data and sets, in a transfer mode setting portion 11, a transfer mode for respectively allocating a first data buffer 16 to a first DMAC 12 and a second data buffer 17 to a second DMAC 13 when parallel ... 10/06/05 - 20050223134 - Accelerated tcp (transport control protocol) stack processing In one embodiment, a method is provided. The method of this embodiment provides performing packet processing on one or more packets, and substantially simultaneously with said performing packet processing, using a data movement module to place one or more payloads corresponding to the one or more packets into a read ... 10/06/05 - 20050223133 - Using a threshold value to control mid-interrupt polling In one embodiment, a method is provided. The method of this embodiment provides performing packet processing on a packet, and placing the packet in a placement queue; if no read buffer is available, determining if the size of the placement queue exceeds a threshold polling value; and if the size ... 10/06/05 - 20050223132 - Communication method and processor A processor has a central processing unit and a first interface. The central processing unit sets a communication parameter in a configuration register in the communication interface. A direct memory access controller or a data transfer controller then sets the same parameter in a register in a communication setup interface ... 10/06/05 - 20050223131 - Context-based direct memory access engine for use with a memory system shared by devices associated with multiple input and output ports A direct memory access (DMA) system provides a single context-based DMA engine connected to the memory system. The context-based DMA Engine implements the logic for each DMA function only once, and switches parameter sets as needed to service various DMA requests from different channels. Arbitration is performed at the DMA ... 10/06/05 - 20050223130 - Data transfer between an external data source and a memory associated with a data processor A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 operable to perform further data processing operations in response to ... 10/06/05 - 20050223129 - Arbitration of data transfer requests A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 ... 10/06/05 - 20050223128 - Accelerated tcp (transport control protocol) stack processing In one embodiment, a method is provided. The method of this embodiment provides receiving an indication on a network component that one or more packets have been received from a network; the network component notifying a TCP-A (transport control protocol—accelerated) driver that the one or more packets have arrived; a ... 10/06/05 - 20050223127 - Logical memory tags for redirected dma operations A memory tag mechanism creates a logical memory tag of a first length that corresponds to an I/O address of a second length. The memory tag is “logical” because it does not represent physical memory. When an I/O adapter device driver that expects an address of the first length is ... 10/06/05 - 20050223126 - Buffer controller between memories and method for the same A buffer controller between a first and a second memories is used to control the buffer during data transmission process for memories. The buffer controller between memories has a microprocessor used to process the data transmission of the memory bus, a first memory connected to the microprocessor, and a second ... 09/29/05 - 20050216615 - Input/output device, computer, computer system, input/output control program, os, page management program, and page management method A computer system including input/output devices that transfer data and a computer that controls a process using a virtual storage and inputs data to and outputs data from a medium, wherein the input/output devices and the computer include address conversion tables for converting a virtual address into an actual address, ... 09/29/05 - 20050216614 - Microcomputer having instruction ram A microcomputer comprises an instruction RAM temporally storing a program transferred from an external memory, a CPU reading out the program from the instruction RAM via a dedicated fetch bus and carrying out a process according to the program, an instruction transfer control circuit directly transferring the program from the ... 09/29/05 - 20050216613 - Tables with direct memory access descriptor lists for distributed direct memory access A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, ... 09/29/05 - 20050216612 - Microcomputer with internal dma A microcomputer has: a CPU; memory; a direct memory access controller which controls access to the above memory without passing through the CPU; a plurality of peripheral resources, each having prescribed functions corresponding to a given real resource number, and issuing an access request to the direct memory access controller ... 09/29/05 - 20050216611 - Method and apparatus to achieve data pointer obfuscation for content protection of streaming media dma engines Embodiments include a system for obfuscating the location of protected data in the memory of a computer system. The system provides a protected mode supported by a memory controller that does not allow the address relating to the location of protected data to be read or accessed. This system may ... 09/29/05 - 20050216610 - Method to provide cache management commands for a dma controller The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling ... 09/29/05 - 20050216609 - Pvdm (packet voice data module) generic bus A generic, parallel, n-bit wide data path communication bus allows a number of major slave devices (such as DSPs, Microprocessors, ASICs, FPGAs, etc) to be used with PVDMs and other devices. A higher level protocol allows a DMA engine to interface multiple Master devices directly with multiple slave modules through ... 09/29/05 - 20050216608 - Multiple channel data bus control for video processing A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In ... 09/22/05 - 20050210163 - Memory control apparatus A memory control section 10 is arranged between a bus 3 and a memory 4, if there is access to a predetermined virtual address space from the bus side, a virtual memory space control section 13 gains the corresponding access to small-capacity FIFO memories 11 and 12 from a memory ... 09/15/05 - 20050204074 - Arbitrating and servicing polychronous data requests in direct memory access Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given ... 09/15/05 - 20050204073 - Arbitrating and servicing polychronous data requests in direct memory access Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given ... 09/08/05 - 20050198411 - Commingled write cache in dual input/output adapter An apparatus, program product and method maintain data coherency between paired I/O adapters by commingling primary and backup data within the respective write caches of the I/O adapters. Such commingling allows the data to be dynamically allocated in a common pool without regard to dedicated primary and backup regions. As ... 09/08/05 - 20050198410 - Method, system and protocol that enable unrestricted user-level access to a network interface adapter A method for preventing deadlock in communication between a host software application and a network interface card (NIC), comprises writing a doorbell associated with at least one descriptor having a descriptor context to a buffer in the NIC, dropping at least one doorbell from the buffer if the buffer is ... 08/25/05 - 20050188121 - System and controller with reduced bus utilization time A memory controller may reduce bus utilization time. The memory controller may include a main controller, a data reading unit, and a serial interface. The main controller may store a control data signal received from a processor through a bus, and may control a memory by generating a request data ... 08/25/05 - 20050188120 - Dma controller having programmable channel priority A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address ... 08/25/05 - 20050188119 - Dma controller for digital signal processors A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address ... 08/18/05 - 20050182865 - System including real-time data communication features A system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another embodiment, the system may also include a medium access control (MAC) to control transmission and reception of the data and that ... 08/18/05 - 20050182864 - Disk controller A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and ... 08/18/05 - 20050182863 - Direct memory access control A direct memory access controller for controlling data transfer between a data source and a data destination comprising: a read/write port operable to receive data from said data source via a source bus and to output said received data to said data destination via a destination bus; wherein said direct ... 08/18/05 - 20050182862 - System and method for detecting dma-generated memory corruption in a pci express bus system A system and method that facilitate detection of direct memory access (DMA) corruption is provided. The system can mitigate DMA memory corruption in computer system(s) employing transaction-based DMA bus system(s) (e.g., PCI Express). DMA transaction(s) cannot normally be traced; however, in accordance with an aspect of the present invention, the ... 08/11/05 - 20050177656 - Method and system for integrating cores in fpga-based system-on-chip (soc) The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to ... 08/11/05 - 20050177655 - Method and apparatus for transporting data sections using a dma controller In a method for transporting (DMA_TASK(n), DMA_TASK(n+1)) data sections between a memory and a peripheral, a control signal (START(n+1)), which is used to ask a DMA controller (DMA) to transport (DMA_TASK(n+1)) a data section, is transmitted to the DMA controller, and information about the data transport operation (DMA_TASK(n+1)) to be ... 08/11/05 - 20050177654 - Display controller, display system, and display control method A display controller includes a frame memory, an interrupt output cycle setting register, and an interrupt signal generation section. The frame memory stores the display data for at least one vertical scan period, the display data being supplied from a host. An output cycle of an interrupt signal to be ... 08/04/05 - 20050172050 - Methods and apparatus for providing data transfer control A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller ... 08/04/05 - 20050172049 - Data processor A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory ... 08/04/05 - 20050172048 - Method for transmitting data via a data bus A method for transferring data via a data bus, in particular via a PCI bus. The method provides for a second additional memory area in which all physical addresses of the memory pages are stored, to be set up in a main memory of an arithmetic-logic unit. During data transfer ... 07/28/05 - 20050165980 - Direct memory access controller system with message-based programming A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable ... 07/21/05 - 20050160202 - Direct memory access device A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word transfers for first and last data of the data and word transfers for all other data; and a transfer unit for ... 07/21/05 - 20050160201 - Apparatus and method for direct memory access in a hub-based memory system A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for ... 07/21/05 - 20050160200 - Processor system, dma control circuit, dma control method, control method for dma controller, graphic processing method, and graphic processing circuit A processor system, comprising: a plurality of arithmetic units capable of performing arithmetic processings in parallel; a storage which stores data that said plurality of arithmetic units use for arithmetic processings; a plurality of DMA controllers which perform data transfer between said plurality of arithmetic units, and between said plurality ... 07/14/05 - 20050154801 - Programming system and method for a video network In a signal processing system, a programming system and method for a video network are provided. An event may trigger an RDMA controller to execute current instructions in a register update list. The triggering event may be a start-of-field signal from a live source or an end-of-frame signal. The current ... 07/07/05 - 20050149645 - Storage control device The invention relates to a storage control device provided with a plurality of channel control sections for receiving data input and output requests from an information processing device and transmitting and receiving data, to and from an information processing device, each of the plurality of channel control sections comprising: an ... 06/30/05 - 20050144337 - Dma prefetch A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one ... 06/30/05 - 20050144336 - Method and apparatus for data sharing A method and an apparatus for directly copying data between multiple memory cards. In the invention data is transferred between various memory cards of different format without occupying memory or a system bus by means of the internal direct memory access (DMA) controller in cooperation with software drivers. ... 06/23/05 - 20050138232 - Memory system control method A memory system control method is a control method in a system which comprises a central processing unit, a cache memory, and a main memory, and has a DMA transfer function to said main memory, wherein when the amount of data transferred to said main memory reaches an arbitrary value, ... 06/09/05 - 20050125572 - Distributed direct memory access for systems on chip A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, ... 06/09/05 - 20050125571 - Virtual first in first out direct memory access device A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO. ... 06/02/05 - 20050120147 - Direct memory access controller enabling cycle stealing among channels A DMAC is provided with a plurality of DMA transfer portions controlling DMA transfer in accordance with values set in a group of registers for current transfer. When the DMAC acquires bus ownership from a bus master, use of the bus is permitted among the plurality of DMA transfer portions ... 06/02/05 - 20050120146 - Single-chip usb controller reading power-on boot code from integrated flash memory for user storage A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a ... ### FreshPatents.com Support |