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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation > Addition/subtraction > Binary BinaryBinary patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230096 - Digital signal processing circuit having an adder circuit with carry-outs An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to ... 10/12/06 - 20060230095 - Digital signal processing circuit having a pre-adder circuit A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and ... 09/14/06 - 20060206557 - Arithmetic logic unit circuit An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, ... 09/14/06 - 20060206556 - Data processing apparatus and method for performing floating point addition A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is ... 08/10/06 - 20060179105 - Long-integer multiplier An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of ... 07/06/06 - 20060149805 - Implementation of digital signal processing functions using maximal efficiency and minimal energy dissipation Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of implementing one or more digital signal processing functions comprises determining one or more parameters associated with generating an optimal logic module. The ... 04/27/06 - 20060089961 - Mixed-type adder comprising multiple sub-adders having different carry propagation schemes Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder is divided into I bit groups which are respectively allocated to the I sub adders. The I ... 03/16/06 - 20060059222 - Logic entity with two outputs for efficient adder and other macro implementations An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for ... 12/29/05 - 20050289211 - One bit full adder with sum and carry outputs capable of independent functionalities A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and ... 12/08/05 - 20050273485 - Polynomial and integer multiplication A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significant bits performing steps (i) to (iii): (i) performing ... 09/22/05 - 20050210095 - Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent. The data processing apparatus comprises ... 09/15/05 - 20050203984 - Digital circuit Disclosed is a digital circuit which comprises input signals A[n−1:0], SH[log2n−1:0], and DAT[n−1:0], a barrel shifter for outputting data B[n−1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation stage for dividing each of the digits of the input signals A and ... 09/15/05 - 20050203983 - Arithmetic circuit with balanced logic levels for low-power operation An adder circuit comprising a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective ... 09/08/05 - 20050198094 - Adder-subtracter circuit The present invention relates to an adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. Furthermore the circuit has the capability to feed back the result ... 09/01/05 - 20050193052 - Apparatus and method for converting, and adder circuit An apparatus and method for converting a dual-rail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output operands have a value which is different from that of the third output operand. In a preparation ... 06/16/05 - 20050131981 - High speed adder design for a multiply-add based floating point unit An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function ... ### FreshPatents.com Support |