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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation > Addition/subtraction Addition/subtractionAddition/subtraction patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/17/06 - 20060184605 - Method of forcing 1's and inverting sum in an adder without incurring timing delay A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. ... 08/10/06 - 20060179103 - System and method for providing a double adder for decimal floating point operations A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second ... 07/20/06 - 20060161614 - N-bit constant adder/subtractor An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the ... 06/22/06 - 20060136543 - Data processing apparatus and method for performing floating point addition A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the ... 05/11/06 - 20060101108 - Using a leading-sign anticipator circuit for detecting sticky-bit information A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sticky bit. However, this design has ... 02/09/06 - 20060031279 - Highly parallel structure for fast multi cycle binary and decimal adder unit An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data ... 02/09/06 - 20060031278 - Multi-value digital calculating circuits, including multipliers Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are ... 01/05/06 - 20060004902 - Reconfigurable circuit with programmable split adder A reconfigurable circuit includes a multiply-accumulator with a programmable pre-adder and also includes a scramble sequence generator. The scramble sequence generator may provide a despreading sequence to control inputs on the programmable pre-adder. ... 10/06/05 - 20050223055 - Method and apparatus to correct leading one prediction A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of ... 09/29/05 - 20050216545 - Simd four-data element average instruction According to some embodiments, a Single-Instruction/Multiple-Data averaging operation is presented. The averaging operation averages multiple sets of data elements, for example, two data elements each from a first source and a second source, producing a set of averages. In at least one embodiment, in a first adder stage, a first ... 09/22/05 - 20050210094 - Method and system to implement an improved floating point adder with integrated adding and rounding Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third ... 09/01/05 - 20050193051 - Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circuit scale and ... ### FreshPatents.com Support |