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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation > Multiplication > Binary BinaryBinary patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060235922 - Quisquater reduction A method and apparatus for calculating the product P of a first number X and a second number Y, modulo N, where Y is partitioned into j words each of length p bits, and has a length (m+n) bits, cyclically operates on successive ones of the j words of Y, ... 10/12/06 - 20060230094 - Digital signal processing circuit having input register blocks An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, ... 06/01/06 - 20060117082 - Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. Multiplier logic is used to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors, and half adder logic ... 06/01/06 - 20060117081 - Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and ... 06/01/06 - 20060117080 - Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. ... 10/06/05 - 20050223054 - Multiplier sign extension method and architecture A multiplier sign extension method and architecture are used for encoding operations of a multiplier of a digital signal processor. The multiplier sign extension method comprises the steps of: determining the width of the multiplier to obtain a sign extension bit total value; encoding a multiplier by means of the ... 09/08/05 - 20050198093 - Montgomery modular multiplier In a Montgomery multiplier, a modulus product generator may select a modulus product from a plurality of selectable n-bit modulus numbers M, a given modulus number M being formed from a currently input extended chunk of bits among the n-bit modulus numbers. A partial product generator may select a multiplicand ... 08/18/05 - 20050182814 - Encoder for a multiplier An encoder of a multiplier may include an operator generating unit for encoding a plurality of received multiplier data to output a plurality of operators. The encoder may include a partial-product data generating unit that generates a sign selecting operator from the received multiplier data for determining signs of the ... 06/30/05 - 20050144217 - Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). ... ### FreshPatents.com Support |