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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation > Multiplication MultiplicationMultiplication patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212506 - Scalar multiplication apparatus and method Example embodiments of the present invention provide a scalar multiplication apparatus and method for a Different Faults Analysis (DFA) countermeasure. The scalar multiplication apparatus and method may include a first encryptor, a second encryptor, a first logic circuit and a logic circuit. The first encryptor may generate a first output ... 09/21/06 - 20060212505 - Low power array multiplier An array multiplier comprises a partial product array including a plurality of array elements and a final carry propagate adder. Operands smaller than a corresponding dimension of the partial product array are shifted toward the most significant row or column of the array to reduce the number of array elements ... 08/31/06 - 20060195503 - Integrated circuit including at least one configurable logic cell capable of multiplication The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial ... 08/24/06 - 20060190519 - Extended precision accumulator A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register ... 08/17/06 - 20060184604 - Arithmetic unit In order to correct an overflow of a multiplication result while improving the operation speed, an overflow detection unit detects an overflow based on whether a multiplicand A and a multiplier B are both a negative value with the largest absolute value. A carry-save adder adds together in carry-save addition ... 08/17/06 - 20060184603 - Zero detect in partial sums while adding The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to ... 06/29/06 - 20060143261 - Method and apparatus for performing a multiplication or division operation in an electronic circuit A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value for K. In a hardware circuit area, the value X is shifted sv digits to the left ... 06/29/06 - 20060143260 - Low-power booth array multiplier with bypass circuits A low-power Booth array multiplier with bypass circuits is provided. The multiplier includes a first encoder for Booth-encoding the multiplier; a second encoder for pre-encoding the multiplier to generate an enabling signal and a plurality of control signals, wherein the control signals are used for determining whether to process partial ... 06/22/06 - 20060136541 - Binary digit multiplications and applications A multiplying system for binary digits. The digits are multiplied in a rectangular memory array, where the digits are placed along the edges, and intersections between 1's form blocks of 1's in the memory array. The blocks of 1's are evaluated based on a weighting assigned to positions within the ... 05/04/06 - 20060095496 - Power of two multiplication engine A multiplication engine is described in which a decision threshold engine utilizes a Y-adder powers of two shift table to iteratively generate shift-add combinations. The shift-add combinations are output in a sequence with decreasing levels of contribution wherein the accuracy of the associated multiplication increases up to any desired level ... 05/04/06 - 20060095495 - Apparatus for hybrid multiplier in gf(2m) and method thereof An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided. The apparatus for hybrid multiplication includes: a matrix Z generation unit generating [m×k] matrix Z ... 03/23/06 - 20060064453 - Modular multiplication with parallel calculation of the look-ahead parameters A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is ... 03/16/06 - 20060059221 - Multiply instructions for modular exponentiation A method and apparatus for increasing performance of a multiplication operation in a processor. The processor's instruction set includes multiply instructions that can be used to accelerate modular exponentiation. Prior to issuing a sequence of multiply instructions for the multiplication operation, a multiplier register in a multiply unit in the ... 02/23/06 - 20060041610 - Processor having parallel vector multiply and reduce operations with sequential semantics A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the ... 01/26/06 - 20060020655 - Library of low-cost low-power and high-performance multipliers Disclosed is an apparatus and method for producing a library of low-cost, low-power multipliers which are easy to build, have self testing capabilities, and are regular. The multipliers multiply a first word having N bits by a second word having M bits and include a plurality of smaller multipliers each ... 01/12/06 - 20060010192 - Apparatus and method for calculating a multiplication An apparatus for calculating a modular multiplication includes an examiner for examining digits of the multiplier with a lookahead algorithm to obtain a multiplication shift value. In addition, a determinator and intermediate-result shift value are provided which determine a positive intermediate-result shift value. A calculator for calculating a multiplicand shift ... 11/03/05 - 20050246407 - High speed multiplication apparatus of wallace tree type with high area efficiency A multiplication array is divided into divided Wallace tree arrays each performing multiplication by addition in a tree-like form. An addition result is transmitted from the divided Wallace tree arrays to a final addition circuit. Thus, an interconnection line length of a critical path of a multiplication apparatus can be ... 08/25/05 - 20050187999 - Saturation and rounding in multiply-accumulate blocks Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation ... 08/18/05 - 20050182813 - Apparatus and method of multiplication using a plurality of identical partial multiplication modules A multiplication apparatus including a multiplier and multiplicand extractor for dividing the multiplicand into partial multiplicands and dividing the multiplier into partial multipliers, and for generating partial input pairs by combining the partial multiplicands with the partial multipliers, and a multiplication executor including identical partial multiplication modules for receiving the ... 07/28/05 - 20050165877 - System, and method for calculating product of constant and mixed number power of two Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer ... 06/30/05 - 20050144216 - Arithmetic circuit with multiplexed addend inputs Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct ... 06/30/05 - 20050144215 - Applications of cascading dsp slices In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal ... 06/23/05 - 20050138102 - Arithmetic unit An arithmetic unit is provided which is capable of enhancing area efficiency while suppressing operating speed reduction. A third partial product adder (T101) is divided into a high order part (T101a) including high-order 12 bits and a low order part (T101b) including low-order 33 bits. The high order part (T101a) ... 06/23/05 - 20050138101 - Methods and apparatus for performing mathematical operations using scaled integers Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-integer value. The multiplier value is determined by extracting information from a first portion ... 06/16/05 - 20050131980 - Logical calculation architecture comprising multiple configuration modes A logical calculation architecture including a multiplicity of configurable calculation components; a multiplicity of interconnection components; a first set of signals that configure the architecture by connecting between the calculation components and the interconnection components; a processor that generates the first set of configuration signals; a multiplicity of configurable control ... 06/09/05 - 20050125480 - Method and apparatus for multiplying based on booth's algorithm A multiplying apparatus and method based on Booth's algorithm are disclosed. According to a multiplier index, a one of several predetermined multiplier coefficient sets can be chosen. Each multiplier coefficient set contains several multiplier coefficients that are generated according to a predetermined multiplier value by Booth's algorithm. Then the multiplier ... 06/09/05 - 20050125479 - Hardware for performing an arithmetic function A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a given estimate to the number. The current estimate is ... 06/09/05 - 20050125478 - Smaller and lower power static mux circuitry in generating multiplier partial product signals A multiplier circuit to receive a multiplier and a multiplicand comprises at least one Booth encoder circuit to encode a plurality of multiplier bits into four encoded outputs. The encoded outputs select Booth-multiply functions. The circuit also includes a plurality of multiplexer circuits, one multiplexer circuit for each bit of ... 06/02/05 - 20050120069 - Dynamically reconfigurable power-aware, highly scaleable multiplier with reusable and locally optimized structures A large bit width multiplier with multiple copies of a core small bit width multiplier and ROM cells. The present invention provides a power system that trades off processing speed against power dissipation. The present invention reduces power dissipation to about half of the best industry implementation at about half ... ### FreshPatents.com Support |