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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation > Multiplication Followed By Addition (i.e., X*y+z) Multiplication Followed By Addition (i.e., X*y+z)Multiplication Followed By Addition (i.e., X*y+z) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/14/06 - 20060206555 - Operation circuit and operation control method thereof A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital ... 08/24/06 - 20060190518 - Binary polynomial multiplier A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. ... 08/03/06 - 20060173946 - Common shift-amount calculation for binary and hex floating point A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the ... 10/20/05 - 20050235025 - Dual-multiply-accumulator operation optimized for even and odd multisample calculations According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed. ... 10/20/05 - 20050235024 - Virtually parallel multiplier-accumulator A virtually parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages. ... 08/25/05 - 20050187998 - Multiplier-accumulator block mode splitting A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used ... 07/28/05 - 20050165876 - Multiple-word multiplication-accumulation circuit and montgomery modular multiplication-accumulation circuit A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. ... 06/30/05 - 20050144214 - Shift-and-negate unit within a fused multiply-adder circuit A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and a group of data signals to generate ... 06/23/05 - 20050138100 - Product-sum operation circuit and method A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand ... ### FreshPatents.com Support |