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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation > Floating Point Floating PointFloating Point patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/17/06 - 20060184601 - Floating point unit with fused multiply add and method for calculating a result with a floating point unit The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with ... 08/10/06 - 20060179099 - System and method for performing decimal floating point addition A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associated with the first operand and the second operand ... 08/10/06 - 20060179098 - System and method for reduction of leading zero detect for decimal floating point numbers A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set ... 08/10/06 - 20060179097 - System and method for a floating point unit with feedback prior to normalization and rounding A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single ... 07/20/06 - 20060161612 - Method and structure for a generalized cache-register file interface with data restructuring methods for multiple cache levels and hardware pre-fetching A method and structure for executing a matrix algorithm requiring an order of N3 operations including data reformatting operations, where N is a dimension of an operand of said algorithm on a computer, includes initially reformatting data for at least one matrix used in the matrix algorithm into a data ... 06/22/06 - 20060136540 - Enhanced fused multiply-add operation An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer k, the exponent of a floating point value A, ... 05/25/06 - 20060112160 - Floating-point number arithmetic circuit Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting ... 05/18/06 - 20060106909 - System and method for mapping mathematical finite floating-point numbers A floating-point number is encoded into a binary string. A left-to-right comparison of the binary string determines relative magnitude of the floating-point number. If the floating-point number is negative, then take an absolute value of the floating-point number. The resulting binary string conversion is then complemented. If the floating-point number ... 03/09/06 - 20060053191 - Floating point encoding systems and methods Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding ... 03/09/06 - 20060053190 - Construction of a folded leading zero anticipator An apparatus, a method, and a computer program are provided for anticipating leading zeros for a Floating Point (FP) computation. Traditional leading zero anticipators (LZA) are typically very wide. To reduce the width of the LZA, it is subdivided to two smaller LZA that compute edge vectors for the most ... 03/02/06 - 20060047739 - Decimal floating-point adder A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and aligns significands associated with the floating-point numbers such that exponents associated with the floating-point numbers ... 12/22/05 - 20050283516 - Apparatus for evaluating a mathematical function Please replace the Specification with the clean copy of the Specification enclosed herewith. No new matter is entered thereby. The enclosed substitute specification is identical to the original specification as filed, except that same incorporates the specification amendment made in the Amendment Before First Office Action dated May 27, 2005. ... 10/27/05 - 20050240645 - Generation of test cases with range constraints for floating point add and subtract instructions Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers {overscore (x)}, {overscore (y)}, {overscore ... 10/06/05 - 20050223053 - Static floating point arithmetic unit for embedded digital signals processing and control method thereof A floating point arithmetic unit for embedded digital signal processing is provided with the ability of tracking the exponent portion of numerals using static analyzing technology efficiently and of low-power consumption. A fix adding unit with a simplified mantissa alignment device and simplified normalizing device arranged at the input end ... 09/22/05 - 20050210093 - Data processing apparatus and method for comparing floating point operands The present invention provides a data processing apparatus and method for comparing first and second floating point operands to produce a comparison result. Each floating point operand has a sign component, an exponent component, and a fraction component. The data processing apparatus comprises first processing logic operable to receive, for ... 08/18/05 - 20050182810 - Fast method for calculating powers of two as a floating point data type A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment supporting a union declaration functionality and a left shift functionality. Accordingly, an input receives an exponent value, and a ... 07/14/05 - 20050154773 - Data processing apparatus and method for performing data processing operations on floating point data elements The present invention provides a data processing apparatus and method for performing data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order ... ### FreshPatents.com Support |