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Electrical Computers: Arithmetic Processing And Calculating > Electrical Digital Calculating Computer > Particular Function Performed > Arithmetical Operation Arithmetical OperationArithmetical Operation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230092 - Architectural floorplan for a digital signal processing circuit A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a ... 10/05/06 - 20060224654 - Method and system for performing digital signal processing operations in a computer system A method and system for performing digital signal processing operations in a computer system are disclosed. Digital Signal Processing operations such as multiply and add (MADD) or multiply and subtract (MSUB) can be performed by general-purpose microprocessors. The DSP operations are directed to n-bit operands that are in m-bit registers. ... 10/05/06 - 20060224653 - Method and system for dynamic session control of digital signal processing operations A method and system for performing digital signal processing operations in a computer system are disclosed. In addition to the ability to perform DSP operation on a new hardware platform, this method and system allow the dynamic and global control of saturation and left shifting prior to accumulation. ... 09/28/06 - 20060218216 - Programmable logic devices with function-specific blocks A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use ... 08/24/06 - 20060190516 - Digital signal processing element having an arithmetic logic unit A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode. ... 07/13/06 - 20060155796 - System and methods for large-radix computer processing Systems and methods for performing large-radix numeric operations. A first number may be segmented into large-radix segments, wherein numbers of the segments are generated such that radix of the segment is greater than radix of the first number. As a result, a plurality of disparate processor-based computing systems may be ... 06/29/06 - 20060143259 - Low power vector summation method and apparatus An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension ... 06/22/06 - 20060136539 - Data processing device with microprocessor and with additional arithmetic unit and associated method In order to further develop a data processing device (100; 100′) having at least one microprocessor (90) and having at least one additional arithmetic unit (40) as well as a method of performing at least one particular defined calculation by means of the data processing device (100; 100′) in such ... 06/15/06 - 20060129623 - Division and square root arithmetic unit A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of ... 05/25/06 - 20060112159 - Processor The present invention provides a processor including data manipulating means for generating an arbitrary combination of elements of a first input vector and elements of a second input vector, arithmetic means for performing a product-sum operation on the combination, and repetition control means for controlling the generation of the combination ... 05/25/06 - 20060112158 - Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism A method and computer program product for estimating total path delay in an integrated circuit design includes steps of: (a) receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design; (b) calculating a sum of the stage delays; (c) calculating ... 05/04/06 - 20060095493 - Equivalent material constant calculation system, storage medium storing an equivalent material constant calculation program, equivalent material constant calculation method, design system, and structure manufacturing method An equivalent material constant calculation system that calculates an equivalent material constant of a structure constituted by a plurality of materials includes a shape data input portion that inputs shape data, a material data input portion that inputs material constant data, a dividing portion that divides the structure into a ... 04/27/06 - 20060089960 - Reducing errors in performance sensitive transformations The invention provides a method, data compression system, apparatus, and article of manufacture which reduce the error in transform equations in which constants are replaced by approximations. According to the invention transform constants are replaced with approximations which are a function of an integer and a floating point value. The ... 04/06/06 - 20060075012 - Efficient implementation of dsp functions in a field programmable gate array An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these ... 04/06/06 - 20060075011 - System and method for optimizing polynomial expressions in a processing environment A method for optimizing polynomial expressions is provided that includes generating kernels in order to form a kernel and co-kernel matrix and generating a cube literal matrix, which includes a plurality of cubes. Rectangles are identified on the kernel and co-kernel matrix and the rectangles are used to find common ... 03/23/06 - 20060064450 - Base four processor A digital signal processing system which samples an analog voltage, converts the sample to a multi digit base four number, performs a computation with this number, using base four arithmetic, and converts the result back to an analog voltage. This system is comprised of a system an analog to digital ... 03/23/06 - 20060064449 - Operation apparatus and operation system The present invention relates to a processing device performing a series of operations on an input and producing an output. An objective of the invention is to provide a processing device that can perform high-speed and flexible processing. According to the invention, the processing device includes multiple arithmetic cells, each ... 03/09/06 - 20060053189 - Graphics processing logic with variable arithmetic logic unit control and method therefor Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data ... 03/09/06 - 20060053188 - Apparatus with redundant circuitry and method therefor An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for ... 03/02/06 - 20060047738 - Decimal rounding mode which preserves data information for further rounding to less precision A method of processing data employs a new rounding mode called “round for reround” on the original arithmetic instruction in the hardware precision, and then 2) invoking an instruction which specifies a variable rounding precision and possibly explicitly sets the rounding mode which we have called the ReRound instruction. The ... 01/26/06 - 20060020653 - Method and system for digital signal processing, program product therefor A system, such as, e.g., a multiplier, for processing digital signals by using digital signals in the Canonic Signed Digit representation, the system including an input element to make the digital signals available in the Binary Canonic Signed Digit representation, a converter to convert the digital signals into Canonic Signed ... 01/26/06 - 20060020652 - Extendable squarer and method of square operation An extendable squarer applied for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n−1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive ... 01/19/06 - 20060015552 - Analog square root calculating circuit for a sampled data system and method A square root calculating circuit is provided for an analog sampled data system. The square root calculating circuit includes a summing integrator circuit and a multiplier circuit. The summing integrator circuit has two inputs wherein the first input is configured to receive an input signal, Vinput. The multiplier circuit is ... 01/19/06 - 20060015551 - Data processing apparatus and scheme for signal measurement A measure system for signal measurement is introduced. The measure system simplifies the effort for a signal measurement in many applications. The application for a signal measurement is, for example, computation of a signal average value. The measure system includes a digital computation circuit together with an analog to digital ... 01/05/06 - 20060004901 - Low-voltage cmos circuits for analog decoders Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its ... 12/08/05 - 20050273483 - Complex logarithmic alu The present invention describes a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a logarithmic format. In one exemplary embodiment, an ALU implements logarithmic arithmetic on complex numbers represented in a logpolar format. According to this embodiment, memory in the ALU stores a look-up ... 10/06/05 - 20050223051 - System for building structured spreadsheets using nested named rectangular blocks of cells to form a hierarchy where cells can be uniquely referenced using non unique names This system is a way of building structured spreadsheets using named nested rectangular block of cells to form a hierarchy. This system allows cells to be referenced by non unique names by using the relative location in the hierarchy of the referenced cell with respect to the cell containing the ... 08/25/05 - 20050187997 - Flexible accumulator in digital signal processing circuitry A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) ... 08/18/05 - 20050182808 - Signal processing method and signal processing circuit A signal processing method includes a first step of calculating a value indicating a value obtained by multiplying a ratio of the number of times of inputting the input signal having any one of values from p to m, where m is a maximum value of values of input signal ... 07/21/05 - 20050160129 - Arithmetic unit for approximating function A look-up table outputs an initial value, an inclination of a straight line and a correction value in response to an entry-of a high-order bit string of an operand. An offset circuit calculates an offset of the low-order bit string. A correction circuit outputs the initial value obtained by adding ... 06/30/05 - 20050144213 - Mathematical circuit with dynamic rounding Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, ... 06/30/05 - 20050144212 - Programmable logic device with cascading dsp slices Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and ... 06/30/05 - 20050144211 - Programmable logic device with pipelined dsp slices Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to ... 06/30/05 - 20050144210 - Programmable logic device with dynamic dsp architecture Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur ... 06/23/05 - 20050138099 - Method and apparatus for averaging parity protected binary numbers A method and an apparatus for averaging includes generating a carry using a least significant bit of each of two binary numbers, wherein the two binary numbers include a first binary number and a second binary number, and adding a first shifted binary number, a second shifted binary number, and ... 06/16/05 - 20050131979 - Apparatus for calculating absolute difference value, and motion estimation apparatus and motion picture encoding apparatus which use the apparatus for calculating the absolute difference value An apparatus calculates an absolute difference value, which facilitates an efficient structure of an SAD calculating unit having a tree-like structure, and a motion estimation apparatus and a motion picture encoding apparatus that use the apparatus that calculates the absolute difference value. By performing calculations after inputting carry-outs output from ... ### FreshPatents.com Support |