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Data Processing: Structural Design, Modeling, Simulation, And Emulation > Simulating Electronic Device Or Electrical System > Circuit Simulation > Including Logic > Event-driven Event-drivenEvent-driven patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/02/06 - 20060247906 - Method for estimating clock jitter for static timing measurements of modeled circuits A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled ... 08/24/06 - 20060190234 - Property generating method, verification method and verification apparatus When a property for verifying a logic system is generated, a list of corresponding events is generated from specifications that the logic system should meet, an event of an undefined state in a first property is extracted from the list of events, and a property representing that the extracted event ... 07/06/06 - 20060149526 - Clock simulation system and method A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; ... 10/13/05 - 20050228629 - Method and a processor for parallel processing of logic event simulation A method and a processor for parallel processing of logic event simulation on circuits comprising a polarity of logic gates, the logic gates having interconnect lines therebetween, the processor (1) further comprising a main processor (2) and an associative memory mechanism (3), the associative memory mechanism (3) comprising a plurality ... 10/06/05 - 20050222832 - Asynchronous clock domain crossing jitter randomiser A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and ... 08/11/05 - 20050177357 - Static timing model for combinatorial gates having clock signal input A method of modeling a combinatorial gate which includes providing a data signal input at the combinatorial gate, providing a clock signal input at the combinatorial gate, propagating the clock signal as an output signal when the output of the combinatorial gate corresponds to the clock signal, and propagating the ... ### FreshPatents.com Support |