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Data Processing: Measuring, Calibrating, Or Testing > Testing System > Of Circuit Of CircuitOf Circuit patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/30/06 - 20060271325 - Smart component-based management techniques in a substrate processing system A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement ... 11/30/06 - 20060271324 - Semiconductor integrated circuit, test method and electronic information device A semiconductor integrated circuit, including: a logic section; an initiating current generating section for generating initiating current for initiating or re-initiating a circuit when the circuit is to be initiated or the circuit operates abnormally; an initiating current detecting section for detecting the initiating current of the initiating current generating ... 11/30/06 - 20060271323 - Method evaluating threshold level of a data cell in a memory device A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; ... 11/23/06 - 20060265172 - Heterogeneous multipath path network test system A test system for a heterogeneous multipath network. A tester system evaluates a plurality of status indicators from a plurality of types of test components in a network. Based on the status indicators of at least one of the test components, the tester system selects a first test to be ... 11/16/06 - 20060259264 - Test apparatus, diagnosing program and diagnosing method therefor There is provided a test apparatus having a plurality of test modules. The test apparatus stores object diagnosing programs for controlling diagnosis of the object test module to be diagnosed of a certain type per type of the test module to be diagnosed and stores, separately from it, a set ... 11/02/06 - 20060247884 - Sensor signal processor A sensor signal processor includes a scale having optically or magnetically fine divisions; a detection sensor that moves with respect to the scale and that is provided in association with the divisions of the scale; and a position detecting unit for calculating positional information by using a counter value of ... 11/02/06 - 20060247883 - A method and system for the interactive testing of assembled wireless communication devices A method and system for the interactive testing of assembled wireless communication devices is provided. The method comprises: assembling the wireless communication devices to include at least one interactive test component for interactively testing the wireless communication device in one or more interactive tests requiring physical actuation or mechanical dynamics ... 11/02/06 - 20060247882 - Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method Acceptability of an electronic device is determined with higher precision by performing testing regarding correlation of the timing at which multiple output signals output from the electronic device change. A test apparatus which tests an electronic device by providing test signals to the electronic device and comparing multiple output signals ... 11/02/06 - 20060247881 - Testing a device under test by sampling its clock and data signal A method of testing a device under test, which is adapted to transmit a digital data signal and a clock signal, the data signal being related to the clock signal, comprising the steps of: sampling within one tester clock cycle of the test device the data signal and the clock ... 11/02/06 - 20060247880 - Testable digital delay line A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay ... 10/26/06 - 20060241887 - Calibration apparatus and method using pulse for frequency, phase, and delay characteristic In a device for measuring the properties of a device under test connected by a signal transmission path having reciprocity, a terminal on the device under test side of the signal transmission path is opened; pulse signals are transmitted to a terminal on the measuring apparatus side of the signal ... 08/31/06 - 20060195287 - Eclipz wiretest for differential clock/oscillator signals A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a ... 08/31/06 - 20060195286 - Apparatus of automatically detecting type of cable connected to network and method thereof The present invention is to provide an apparatus of automatically detecting the type of a cable connected to a network and method thereof, which comprising a memory having an automatic detection program, a switch, a network controller adapted to switch the state of the switch based on a predetermined switching ... 08/31/06 - 20060195285 - Canary device for failure analysis A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted ... 08/24/06 - 20060190208 - System and method for testing a memory A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, ... 08/24/06 - 20060190207 - Pattern detection for integrated circuit substrates A method for selecting test site locations on a substrate, by a) specifying a subset of all test site locations on the substrate, and b) selecting a desired number of candidate test site locations from within the subset of test site locations on the substrate. c) While selecting one of ... 08/24/06 - 20060190206 - Semiconductor test management system and method A system and method for semiconductor test management. A second computer receives a scrap rule from a first computer, acquires an initial scrap threshold corresponding to the scrap rule, stores the scrap rule as a SBC/SBL (Statistic BIN Control/Statistic BIN Limit) rule when a scrap condition therein is less or ... 07/27/06 - 20060167645 - Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (ic) An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing ... 07/13/06 - 20060155500 - Ic with on-board characterization unit A system and method for providing a built-in characterization of a semiconductor device (201). The device is provided with a built-in, integral, characterization unit (203) which allows characterization of the device without the need for external test equipment. ... 07/06/06 - 20060149492 - System and method for testing differential signal crossover using undersampling System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a device under test (DUT) and an automatic test equipment (ATE). The test circuit comprises a pair of window comparators coupled to a differential mode signal from the DUT, ... 06/29/06 - 20060142967 - System and method for fault indication on a substrate in maskless applications A method and system for fault indication on a substrate. A method of the present invention includes the following steps. It is determined whether data includes at least one suspicious bit. A pattern generator is controlled with the data. A beam of radiation is patterned using the pattern generator. Features ... 06/01/06 - 20060116840 - Apparatus and method for testing non-deterministic device data A method and system is provided for detecting and correcting non-deterministic data that provides substantially real-time validation results and maximizes flexibility for the device manufacturer while reducing test costs. The automatic test apparatus and method can correct non-determinism caused by cycle slipping at the beginning of data transmission, between packets ... 05/25/06 - 20060111864 - Printhead assembly with composite support beam for a pagewidth printhead A pagewidth printhead assembly that includes a support beam assembly having a composite shell of metals selected so that the shell has a coefficient of thermal expansion substantially the same as that of silicon and a core located within the shell and defining a number of longitudinally extending ink reservoirs ... 05/25/06 - 20060111863 - Method of automatic adjustment of the control parameters of a magnetic suspension system In adjustment of the control parameters of a magnetic suspension system, an object of the present invention is to provide a technique for adjusting the control parameters to optimum values automatically by employing the iterative feedback tuning method, without increasing the complexity of the program, the amount of calculation and ... 05/18/06 - 20060106563 - Method and system of generic implementation of sharing test pins with i/o cells The present invention provides a method and a system of generic implementation of sharing test pins with I/O cells. The method includes a step of making a general change in a testlib file. The testlib file is suitable for controlling I/O cell pins to gain test access. The general change ... 05/11/06 - 20060100814 - Automated circuit board test actuator system A method for automatically inserting connectors and coupling test probes to circuit boards, such as computer system boards and the like. The method is implemented via an apparatus that enables connectors to be automatically inserted into mating connectors on a circuit board device under test (DUT). Connectors may be automatically ... 05/11/06 - 20060100813 - Automated circuit board test actuator system An apparatus for automatically inserting connectors and coupling test probes to circuit boards, such as computer system boards and the like. The apparatus enables connectors to be automatically inserted into mating connectors on a circuit board device under test (DUT). Connectors may be automatically inserted along 1-4 axes. The apparatus ... 05/11/06 - 20060100812 - Low cost test for ic's or electrical modules using standard reconfigurable logic devices Low cost test for Integrated Circuits or electrical modules using a reconfigurable logic device is described. In one embodiment, the invention includes configuring a reconfigurable logic device to comply with input standards of a device under test, applying test signals to the device under test, detecting output results of the ... 05/11/06 - 20060100811 - Method and apparatus for rapid inline measurement of parameter spreads and defects in integrated circuit chips A method and apparatus for monitoring a plurality of semiconductor devices is disclosed. At least one array of 2n semiconductor circuits is provided. A clock ring oscillator provides a clock signal. The clock signal drives a frequency divider followed by an n-stage binary counter. The outputs from the counter's stages ... 05/11/06 - 20060100810 - Testing of integrated circuits An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell (14) is also coupled between a respective one of the terminals (16) and the core circuit (10). A ... 04/13/06 - 20060080058 - Built-in self test for memory interconnect testing In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, ... 04/06/06 - 20060074583 - Methods and systems for unattended tracking of device transfer rates and reporting of performance degradation An operating system's input/output control (IOCTL) interface can communicate with one or more device drivers, which may be implemented as Message Passing Technology (MPT) based drivers. At start-up and at user-defined intervals, Message Passing Interface (MPI) pass-through messages can be sent utilizing the IOCTL interface. Such messages can be formatted ... 04/06/06 - 20060074582 - Network analyzer applying loss compensation using port extensions and method of operation In one embodiment, a method of operating a network analyzer, comprises applying a stimulus signal on at least one port of the network analyzer for provision to a device under test (DUT) within a test fixture coupled to the network analyzer; generating measurement data from the DUT in response to ... 03/23/06 - 20060064268 - Dynamic creation and modification of wafer test maps during wafer testing Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test results are dynamically obtained and examined ... 03/23/06 - 20060064267 - Signal processing system for sensor A signal processing system for a sensor for judging whether an event to be detected has occurred on the basis of a frequency of a sensor output includes a converting device for converting the sensor output into a square wave, a presuming device for presuming whether the frequency of the ... 03/23/06 - 20060064266 - Method and system for the interactive testing of assembled wireless communication devices A method for testing wireless communication devices in stages in a production line for the assembly of said devices, comprises assembling each respective wireless communication device such that each device includes an interactive test component for interactively testing the device; and testing each device using the interactive test component at ... 03/23/06 - 20060064265 - System and method for burn-in test control Systems and methods for controlling test conditions using logic built-in self-test (LBIST) components to affect test conditions. In one embodiment, an LBIST controller is coupled to LBIST circuitry that is incorporated into the design of a device under test, and also to a thermal sensor that is in thermal communication ... 03/09/06 - 20060052964 - Test apparatus and testing method A test apparatus that tests a device under test, includes: a main memory having an expectation pattern storing region storing an expectation pattern sequence to be sequentially compared with a plurality of output patterns sequentially output from a terminal of the device under test; a test pattern outputting unit operable ... 03/02/06 - 20060047460 - Method for testing image processing circuit, particle image analyzer, and storage medium A particle image analyzer provided with an image processor for executing predetermined image processes on a particle image containing an image of a particle, a reading means for reading test result data from a flash memory card on which are previously recorded test result data equivalent to the processing result ... 03/02/06 - 20060047459 - Edge-aligned ratio counter An Edge-Aligned Ratio Counter (EARC) that includes at least one processor coupled to at least one counter circuit is provided for determining a ratio between two clock signals by receiving a first and a second value in response to a first clock signal and generating a control signal under control ... 03/02/06 - 20060047458 - Smart component-based management techniques in a substrate processing system A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement ... 02/23/06 - 20060041397 - Method for checking a integrated circuit for electrostatic discharge bobustness The invention is a method and a computer program product for checking an integrated circuit for electrostatic discharge (ESD) robustness at the design level and comprises essentially the check of the layout of the integrated circuit against a set of rules defining one or more transistor geometric and/or electrical and/or ... 02/16/06 - 20060036391 - System and method for testing cmos image sensor The invention relates to a system and method for testing CMOS image sensor. The system for testing CMOS image sensor comprises: a test supporter, a light source controller, an interface card and an image processor. The test supporter is used to support a CMOS image sensor under test. The light ... 02/16/06 - 20060036390 - Method and apparatus for configuration of automated debug of in-circuit tests A method for configuring an automated in-circuit test debugger is presented. The novel test debug and optimization configuration technique configures expert knowledge into a knowledge framework for use by an automated test debug and optimization system for automating the formulation of a valid stable in-circuit test for execution on an ... 02/09/06 - 20060031036 - Apparatus and method for measuring characteristics of dynamic electrical signals in integrated circuits Systems and methods consistent with principles of the present invention allow contactless measurements of voltage characteristics of dynamic electrical signals in integrated circuits. The invention utilizes a signal analysis circuit, such as a voltage comparator, disposed with the circuit under test, which is optically coupled with the external timing measurement ... 02/02/06 - 20060025955 - Gas density transducer A gas density transducer including: a piezoresistive bridge sensor operative to provide an output indicative of an applied pressure, a computing processor having multiple inputs and at least one output, with the output of the bridge sensor coupled to an input of the processor; a temperature sensor coupled to an ... 02/02/06 - 20060025954 - Process variation detector and process variation detecting method A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a ... 01/26/06 - 20060020412 - Analog waveform information from binary sampled measurements Circuits that count zeros or ones in a binary sampling of a signal can measure analog characteristics of the signal. By this technique, relatively simple circuits can perform parameter measurements that are difficult to achieve with BER-based binary sampling techniques. Low cost binary sampling circuits can also perform measurements that ... 01/26/06 - 20060020411 - Built-in self-test emulator Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST ... 01/19/06 - 20060015283 - Method to extract gate delay parameter in high frequency circuits The present invention provides for determining gate speed parameters in a circuit. A first delay is selected. A second delay is selected, wherein the second delay is longer than the first delay. A clock signal is delayed as a function of the first delay. The clock signal is combined with ... 01/05/06 - 20060004534 - Increased yield manufacturing for integrated circuits A system and method for providing increased manufacturing yield for integrated circuits. Various aspects of the invention may comprise receiving an integrated circuit designed to operate at nominal power supply characteristics. The integrated circuit may, for example, be tested at nominal power supply characteristics to determine if the integrated circuit ... 01/05/06 - 20060004533 - Mcu test device A testing device for testing integrated circuits is disclosed including a first board configured to connect to a specific integrated circuit being tested. A second board is removably connected to the first board and is configurable to test a variety of integrated circuits. An MCU located on the second board ... 12/15/05 - 20050278133 - Integrated test circuit A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of ... 12/08/05 - 20050273290 - Method for evaluating semiconductor device The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality ... 12/01/05 - 20050267706 - Increase productivity at wafer test using probe retest data analysis Disclosed is a method and system for wafer/probe testing of integrated circuit devices after manufacture. The invention begins by testing an initial group of devices (e.g., integrated circuit chips) to produce an initial failing group of devices that failed the testing. The devices in the initial failing group are identified ... 11/24/05 - 20050261856 - Carrier module for adapting non-standard instrument cards to test systems A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier ... 11/10/05 - 20050251358 - System and method for increasing die yield The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in ... 11/03/05 - 20050246127 - Integrated process condition sensing wafer and data analysis system A process condition measuring device and a handling system may be highly integrated with a production environment where the dimensions of the process condition measuring device are close to those of a production substrate and the handling system is similar to a substrate carrier used for production substrates. Process conditions ... 11/03/05 - 20050246126 - Method, apparatus and computer program product for implementing physical interconnect fault source identification A method, apparatus and computer program product are provided for implementing physical interconnect fault source identification. Interconnect test data are processed and each unique failing chip combination is identified. Each common failing chip of the identified unique failing chip combinations is identified. A selected probability failure is reported for each ... 11/03/05 - 20050246125 - System and method of digitally testing an analog driver circuit A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal ... 11/03/05 - 20050246124 - Device and system for recording the motion of a wafer and a method therefrom The invention provides a device that can be used to record the motion of a wafer and fine perturbations and vibrations in its motion during its progress through and between semiconductor process and inspection machines in the course of the actual manufacturing process or during a test cycle of the ... 10/06/05 - 20050222796 - Method for testing an integrated semiconductor memory with a shortened reading time An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by ... 10/06/05 - 20050222795 - Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (ic) An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing ... 09/22/05 - 20050209808 - Circuit board diagnostic operating center A circuit board diagnostic operating center (10) including a large flat panel display (18) used for displaying the test system assets (instruments 12) and the circuit card assembly (CCA) schematic diagram, a small flat panel display (20) to display ancillary information, a computer (24) that executes the system application program ... 08/18/05 - 20050182587 - Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon A circuit quality evaluation method obtains an indicator linked to the quality of a circuit by applying information representing a minimum delay margin of a path passing through an assumed fault site, a machine cycle, and a delay fault occurrence frequency. Further, the circuit quality evaluation method evaluates the quality ... 08/18/05 - 20050182586 - Digital circuit for frequency and timing characterization A digital circuit operating frequency characterizer provides a combination of frequency and duty cycle characterization. The digital circuit operating frequency characterizer includes a programmable frequency generator, a programmable edge variator, a test engine, and a control circuit. The programmable frequency generator provides one or more output signals, and the programmable ... 08/18/05 - 20050182585 - Structure and method for package burn-in testing The present invention discloses a contact structure and method for burn-in testing. The structure comprises a print circuit board, metal solder join fixed to the print circuit board, and contact fixed plate. The contact metal springs are located on the metal solder join and contacted with contact metal balls. The ... 08/18/05 - 20050182584 - Method and system for identifying and locating defects in an integrated circuit A method and system for detecting and locating defects in an integrated circuit. A time-varying input signal is applied to the integrated circuit, power signals produced at a plurality of respective ordered connections in response to the input signal are measured, and one or more defects in the integrated circuit ... 08/18/05 - 20050182583 - Testing apparatus A testing apparatus having a plurality of testing module slots onto which different types of testing modules are optionally mounted includes a plurality of controlling modules for supplying a control signal to each of the testing modules, the testing modules being mounted on the testing module slots respectively, the control ... 08/11/05 - 20050177334 - Resistance value calculation method The resistance value of a supply line (Rline), the resistance value of a decoupling capacitor (Rcap), and the resistance value of a transistor (Rmos) are separately calculated from mask layout information 31 of a semiconductor integrated circuit. The resistance value between external terminals (Ri) is calculated from the resistance value ... 08/04/05 - 20050171718 - Apparatus for testing a device with a high frequency signal The present invention provides an apparatus for testing a device with a high frequency signal, such as an RF signal. The apparatus delivers a high frequency signal directly to a loadboard with a coaxial cable. The coaxial cable can deliver the signal to a location at or near the device ... 08/04/05 - 20050171717 - Method and apparatus for creating variable delay Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response ... 08/04/05 - 20050171716 - Attenuator test system System for testing attenuators by a flatness and standing wave ratio tests which includes a vector network analyzer (VNA) adapted to be coupled to a device under test (DUT) and which provides an input stimulus signal for the DUT and, when certain conditions are satisfied, receives an output signal from ... 07/28/05 - 20050165572 - Systems and methods for non-intrusive testing of signals between circuits Structures and methods for non-intrusive testing of communication signals exchanged between two circuit boards via an intermediate interconnect board. In one aspect hereof, test signals are exchanged between the two circuit boards without requiring active circuits on the interconnect board. In another aspect hereof, the functional signal normally exchanged between ... 06/30/05 - 20050143946 - Method and apparatus for head write capability measurement in self test A method of determining the write head capacity during self test of a hard disk drive is described. Information related to the dynamic coercivity of the disk service is obtained. In one embodiment, a DC erase condition is produced onto the disk surface. An AC signal is provided to a ... 06/30/05 - 20050143945 - Automatic exchange of degraders in accelerated testing of computer chips Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam ... 06/09/05 - 20050125184 - Method and apparatus for monitoring integrated circuit fabrication In one aspect, the present invention is a sensor unit for sensing process parameters of a process to manufacture an integrated circuit using integrated circuit processing equipment. In one embodiment, the sensor unit includes a substrate having a wafer-shaped profile and a first sensor, disposed on or in the substrate, ... ### FreshPatents.com Support |