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Semiconductor Device Manufacturing: Process > Chemical Etching > Combined With Coating Step Combined With Coating StepCombined With Coating Step patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082494 - Method for forming silicide layer A method for forming a metal silicide over a substrate is provided. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system ... 04/12/07 - 20070082493 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, includes forming a sacrifice film on an etching target film, forming an etching mask on the sacrifice film, etching the etching target film using the etching mask as a mask, removing the sacrifice film to allow the etching mask to adhere to the ... 04/12/07 - 20070082492 - Semiconductor memory device and method of fabricating the same A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of ... 04/05/07 - 20070077765 - Etch stop and hard mask film property matching to enable improved replacement metal gate process A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard ... 03/29/07 - 20070072428 - Method for manufacturing a micro-electro-mechanical structure A technique for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided. Next, a plurality of trenches are etched into the substrate with a first etch. Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches. ... 03/22/07 - 20070066068 - Method of depositing a layer comprising silicon, carbon, and flourine onto a semiconductor substrate The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing ... 03/22/07 - 20070066067 - Method for reducing foreign material concentrations in etch chambers A method of reducing foreign material concentrations in an etch chamber having inner chamber walls is described. The method includes the step of etching a work piece in the etch chamber such that reaction products from the work piece having one or more elements form a first layer of reaction ... 01/04/07 - 20070004212 - Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device A method for manufacturing a semiconductor substrate comprises, forming a first semiconductor layer on a part of a surface of a semiconductor substrate, implanting a speed improvement factor to improve an etching speed and a diffusion inhibitor to inhibit diffusion of the speed improvement factor into the first semiconductor layer, ... 12/28/06 - 20060292879 - Method for peeling off semiconductor element and method for manufacturing semiconductor device A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions ... 12/28/06 - 20060292878 - Method for fabricating semiconductor element A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes the steps of: preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide ... 12/28/06 - 20060292877 - Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the ... 12/14/06 - 20060281318 - Method of manufacturing semiconductor device Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been obtained. In the case of operating a CPU with high-speed, the length of a gate (gate length) of a TFT is ... 12/14/06 - 20060281317 - Thin film transistor substrate and method of fabricating the same The invention relates to a thin film transistor substrate for use in a liquid crystal display device and a method of fabricating the same, and an object is to provide a thin film transistor substrate which can ensure high reliability even though a low resistance metal is used in a ... 12/14/06 - 20060281316 - Semiconductor device and method of manufacturing the same A semiconductor device manufacturing method, includes a step of forming a first alumina film (underlying insulating film) 37 on a semiconductor substrate 20, a step of forming a first conductive film 41, a ferroelectric film 42, and a second conductive film 43 in sequence on the first alumina film 37, ... 11/23/06 - 20060264053 - Method of aligning nanotubes and wires with an etched feature A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of ... 11/16/06 - 20060258159 - Process for preparing electronics structures using a sacrificial multilayer hardmask scheme A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then ... 11/02/06 - 20060246728 - Etching method using an at least semi-solid media An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting ... 11/02/06 - 20060246727 - Integrated dual damascene clean apparatus and process An integrated apparatus comprises a plasma etching station, a wet cleaning station, a de-gassing station, a thin film deposition station, and a wafer transfer mechanism to automatically index wafers between the stations in a predetermined processing order. ... 10/12/06 - 20060228892 - Anti-reflective surface A discontinuous layer is formed on a transparent substrate of a semiconductor material. Portions of the transparent substrate are exposed at discontinuities in the discontinuous layer. The discontinuous layer and the exposed portions of the transparent substrate are etched at least until the discontinuous layer is completely removed, thereby forming ... 10/05/06 - 20060223321 - High-density plasma (hdp) chemical vapor deposition (cvd) methods and methods of fabricating semiconductor devices employing the same In one embodiment, a semiconductor substrate is placed into a process chamber. A gas mixture including a silicon-containing gas, a fluorine-containing gas, an inert gas, and an oxygen gas is introduced into the chamber at a pressure range of from about 30 mTorr to about 90 mTorr. During this time, ... 09/14/06 - 20060205221 - Method to modulate etch rate in slam Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This particularly useful in a dual damascene process where the SLAM fills a via opening and is etched along ... 09/14/06 - 20060205220 - Stabilized photoresist structure for etching process A method for forming features in an etch layer is provided. A first mask is formed over the etch layer where the first mask defines a plurality of spaces with widths. The first mask is laterally etched where the etched first mask defines a plurality of spaces with widths that ... 08/24/06 - 20060189142 - Method for making a sub-micron solid oxide electrolyte membrane This document describes fabrication method for a thin film electrolyte membrane and electrochemical devices including the membrane. As an electrolyte becomes thinner, the conductance of the electrolyte increases. Consequently, the performances of solid-state ionic devices like fuel cells, gas sensors and catalytic supporters, can be improved and operating temperature can ... 08/24/06 - 20060189141 - Solution for etching copper surfaces and method of depositing metal on copper surfaces A solution for etching copper or a copper alloy for producing a copper surface having the brightest possible finish for a metallization that is to follow is described. The solution has a pH on the order of 4 or less and is free of sulfate ions. It comprises: a) at ... 07/06/06 - 20060148262 - Method for fabricating microelectromechanical optical display devices A Method of forming microelectromechanical optical display devices is provided. A sacrificial layer is formed above a substrate. A plurality of posts penetrating the sacrificial layer is formed. A reflective layer and a flexible layer are sequentially formed above the sacrificial layer and the posts. A photoresist layer is formed ... 06/29/06 - 20060141793 - Forming of trenches or wells having different destinations in a semiconductor substrate A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening ... 06/22/06 - 20060134918 - Manufacturing method of substrate having conductive layer and manufacturing method of semiconductor device The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer, forming a low wettability layer with respect to a composition containing conductive particles on ... 06/22/06 - 20060134917 - Reduction of etch mask feature critical dimensions A method for forming features in an etch layer in an etch stack with an etch mask over the etch layer, wherein the etch mask has etch mask features with sidewalls, where the etch mask features have a first critical dimension, is provided. A cyclical critical dimension reduction is performed ... 06/15/06 - 20060128155 - Columnar structured material, electrode having columnar structured material, and production method therefor To obtain a microcolumnar structured material having a desired material. The columnar structured material includes columnar members 15 obtained by introducing a filler into columnar holes formed in a porous material. The porous material has the columnar holes 14 formed by removing columnar substances from a structured material in which ... 06/08/06 - 20060121738 - Method of treating conductive layer for use in a circuitized substrate and method of making said substrate having said conductive layer as part thereof A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used ... 06/08/06 - 20060121737 - Method of manufacturing a semiconductor device and method of manufacturing a thin layer using the same A method includes providing a first distance between an inlet of a line and a chuck for supporting a substrate. A first material is applied to the substrate on the chuck through the line to process the substrate. A second distance is provided between the inlet of the line and ... 05/04/06 - 20060094243 - Compositions including perhydro-polysilazane used in a semiconductor manufacturing process and methods of manufacturing semiconductor devices using the same Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index of about 1.8 to about 3.0 are provided. Solutions comprising the compositions of the present invention, methods of forming films in a semiconductor ... 04/27/06 - 20060089002 - Method to form etch and/or cmp stop layers In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A ... 04/27/06 - 20060089001 - Localized use of high-k dielectric for high performance capacitor structures Techniques are provided for localized use of high-K dielectric material within a capacitor structure. Low-K dielectric is deposited or spun on as usual. Then, a larger area is etched back and then filled with high-K dielectric material. The high-K dielectric material is then patterned and copper routing lines are trenched ... 04/20/06 - 20060084273 - Semiconductor device using damascene technique and manufacturing method therefor A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and ... 03/16/06 - 20060057851 - Method for fabricating fine features by jet-printing and surface treatment A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature ... 03/02/06 - 20060046492 - Methods and forming structures, structures and apparatuses for forming structures Methods of forming a contact structure, contact structures and apparatuses applied thereto are disclosed. The method of forming a contact structure forms a dielectric layer on a substrate. A metal contact with metal oxide thereon is formed in the dielectric layer. The solubility of the metal oxide is enhanced by ... 02/16/06 - 20060035466 - Method for manufacturing plasma display panels A method for manufacturing a plasma display panel including a dielectric layer that is formed by a vapor deposition method and covers electrodes except their terminal portions, includes the steps of depositing a dielectric on a substrate on which each of the electrodes having a terminal portion at an end ... 01/05/06 - 20060003588 - Flash memory cells with reduced distances between cell elements An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 ... 12/15/05 - 20050277299 - Methods for fabricating read sensor for magnetic heads with reduced read track width The fabrication of the read head sensor components where chemical mechanical polishing (CMP) stop layer is deposited above the sensor layers, a first reactive ion etch (RIE) layer and a second RIE layer are deposited, where the second RIE layer is etchable with a different ion species than the first ... 09/15/05 - 20050202680 - Method for shrinking a dimension of a gate A method for shrinking a dimension of a gate is provided that utilizes a thermal oxidation to form an oxide layer on a semiconductor substrate and a gate. Controlling the thickness of the oxide layer on the gate will control the channel length of a gate. The oxide layer on ... 09/15/05 - 20050202679 - Method for manufacturing a photonic device and a photonic device The present invention relates to a photonic device including a first device comprising a first set of layers, including at least a first waveguide layer, arranged in a mesa structure, and a second set of layers, including at least a second waveguide layer, formed in a second device region coupled ... 08/25/05 - 20050186800 - Self-masking defect removing method A method for removing defects from a semiconductor surface is disclosed. The surface of the semiconductor is first coated with a protective layer, which is later thinned to selectively reveal portions of the protruding defects. The defects are then removed by etching. Finally, also the protective layer is removed. According ... 08/11/05 - 20050176255 - Electronic package repair process A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of ... 08/11/05 - 20050176254 - Pattern forming method and manufacturing method of semiconductor device A pattern forming method comprises forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy ... 07/14/05 - 20050153562 - Method of independent p and n gate length control of fet device made by sidewall image transfer technique Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that ... 07/07/05 - 20050148188 - System and method for monitoring particles contamination in semiconductor manufacturing facilities Provided is a particle monitoring system capable of detecting a level of polymer particle contamination on inner walls of a process chamber. Also disclosed is a method of monitoring the level of polymer particle contamination on inner walls of a process chamber. ... 06/16/05 - 20050130432 - Method for improving transistor leakage current uniformity Methods are described for fabricating semiconductor devices and transistors thereof, in which a patterned gate length is measured and offset spacers are formed along the sides of the patterned gate prior to drain extension implants, wherein the offset spacer width is controlled according to the measured gate length. This facilitates ... 06/16/05 - 20050130431 - Method for making a package substrate without etching metal layer on side walls of die-cavity A method for making a package substrate without etching metal layer on side walls of a die-cavity is disclosed. At least a through slot is formed around a defined die-cavity region of a substrate so as to form a die-cavity portion in the die-cavity region. The through slot has side ... 06/09/05 - 20050124166 - In situ application of etch back for improved deposition into high-aspect-ratio features A continuous in situ process of deposition, etching, and deposition is provided for forming a film on a substrate using a plasma process. The etch-back may be performed without separate plasma activation of the etchant gas. The sequence of deposition, etching, and deposition permits features with high aspect ratios to ... 06/02/05 - 20050118825 - Process for producing group iii nitride compound semiconductor A method including the steps of: modifying at least one part of a sapphire substrate by dry etching to thereby form any one of a dot shape, a stripe shape, a lattice shape, etc. as an island shape on the sapphire substrate; forming an AlN buffer layer on the sapphire ... ### FreshPatents.com Support - Terms & Conditions |