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Semiconductor Device Manufacturing: Process > Chemical Etching Chemical EtchingChemical Etching patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087568 - Apparatus for etching wafer by single-wafer process and single wafer type method for etching wafer An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating ... 04/12/07 - 20070082489 - Method of fabricating openings and contact holes A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the ... 04/05/07 - 20070077763 - Deposition technique to planarize a multi-layer structure The present invention is directed to a method of coating a substrate having a solidified layer formed thereon, that features depositing a flowable material upon the solidified layer and forming an additional layer having a smooth flowable surface upon the substrate by imparting rotational movement upon the substrate followed by ... 03/29/07 - 20070072423 - Unpolished semiconductor wafer and method for producing an unpolished semiconductor wafer Unpolished semiconductor wafers are produced by: (a) pulling a single crystal of a semiconductor material, (b) grinding the single crystal round, (c) separating a semiconductor wafer from this crystal, (d) rounding the edge of the semiconductor wafer, (e) surface-grinding at least one side of the semiconductor wafer, (f) treating the ... 03/29/07 - 20070072422 - Hydrogen treatment to improve photoresist adhesion and rework consistency A process for selectively removing photoresist, organic overlayers, and/or polymers/residues from a substrate without altering the surface chemistry and adhesion properties of the underlying substrate layers is provided. Generally, the process includes pretreating the substrate with hydrogen (e.g., by way of a hydrogen-based plasma) prior to deposition of a photoresist ... 03/29/07 - 20070072421 - Method to passivate defects in integrated circuits Defects in an integrated circuit are electrically passivated. A hydrogen diffusion blocking film is placed on the integrated circuit. Atomic hydrogen is implanted through the hydrogen diffusion blocking film. The integrated circuit is annealed so that the implanted atomic hydrogen diffuses towards locations where the defects are concentrated. ... 03/22/07 - 20070066064 - Methods to avoid unstable plasma states during a process transition In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by ... 03/22/07 - 20070066063 - Method for chemical mechanical planarization of a metal layer located over a photoresist layer and a method for manufacturing a micro pixel array using the same The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal layer, without limitation, may include the steps of forming a metal layer over a photoresist layer, and then planarizing the metal layer using a ... 03/22/07 - 20070066062 - Landing uniformity ring for etch chamber A novel landing uniformity ring for an etch chamber is disclosed. The landing uniformity ring includes an annular ring body defining a ring opening and an increased-diameter inner flange extending inwardly from the ring body, into the ring opening. When mounted in a landing uniformity ring assembly, the inner flange ... 03/15/07 - 20070059934 - Methods of forming fine patterns, and methods of forming trench isolation layers using the same Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the ... 03/15/07 - 20070059933 - Plasma ashing method A plasma ashing method is used for removing a patterned resist film in a processing chamber after etching a portion of a low-k film from an object to be processed in the processing chamber by using the patterned resist film as a mask. The method includes a first step of ... 03/08/07 - 20070054493 - Methods of forming patterns using phase change material and methods for removing the same In a method of forming patterns using a phase change material layer a phase change material layer may be formed, and selectively phase-changed along a pattern using an exposure beam or other heat source. A phase change material layer pattern may be formed by selectively removing phase-changed portions using a ... 03/08/07 - 20070054492 - Photoreactive removal of ion implanted resist A method for removing ion implanted photoresist from a surface of a substrate is provided. The method may include introducing a gas to a reaction chamber containing the substrate; illuminating the ion implanted photoresist with radiation from a laser in the presence of the gas; and scanning the radiation across ... 03/08/07 - 20070054491 - Wafer cleaning process The invention is directed to a wafer cleaning process for being applied on a wafer after an etching process is performed on the wafer, wherein the wafer has a wafer center, a wafer radius and a wafer circumference. The wafer cleaning process comprises a step of dispensing a cleaning solution ... 03/08/07 - 20070054490 - Semiconductor process for preventing layer peeling in wafer edge area and method for manufacturing interconnects A semiconductor process for preventing the layer on a wafer edge from peeling is provided. First, a dielectric layer is formed on the front side of a substrate. Then, a photoresist layer is formed to cover the front side and part of the backside of the substrate. Thereafter, an edge ... 03/01/07 - 20070049031 - Etching method, method of fabricating metal film structure, and etching structure There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a substrate, a protective film formed on the ... 03/01/07 - 20070049030 - Pitch multiplication spacers and methods of forming the same Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the ... 03/01/07 - 20070049029 - Method of etching a te/pcmo stack using an etch stop layer A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the ... 03/01/07 - 20070049028 - Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed ... 02/22/07 - 20070042604 - Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L≦0.8; 0<M≦0.25; 0<N≦0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used ... 02/22/07 - 20070042603 - Method for etching having a controlled distribution of process results Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to ... 02/22/07 - 20070042602 - Etch method using supercritical fluids Methods are described for removing a material from a substrate by dissolving an etchant into a solvent to form a solution; and exposing the substrate to the solution so that the etchant in the solution removes material from the substrate; wherein during the exposure the solution is maintained in a ... 02/22/07 - 20070042601 - Method for etching high dielectric constant materials In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having ... 02/15/07 - 20070037396 - Semiconductor processing using energized hydrogen gas and in combination with wet cleaning A method of fabricating a semiconductor device. The method comprises subjecting a substrate having formed thereon photoresist layer to a plasma hydrogen, the substrate further having formed thereon a sacrificial layer; contacting the photoresist layer with a photoresist removal solution; subjecting the sacrificial layer to a plasma hydrogen; and contacting ... 02/15/07 - 20070037395 - Stringer elimination in a bicmos process A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a ... 02/08/07 - 20070032082 - Semiconductor substrate process using an optically writable carbon-containing mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask, the method includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be exposed to a light source in accordance with a predetermined pattern, depositing ... 02/08/07 - 20070032081 - Edge ring assembly with dielectric spacer ring An edge ring assembly surrounds a substrate support surface in a plasma etching chamber. The edge ring assembly comprises an edge ring and a dielectric spacer ring. The dielectric spacer ring, which surrounds the substrate support surface and which is surrounded by the edge ring in the radial direction, is ... 02/01/07 - 20070026678 - Wet etchable laminated body, insulation film, and electronic circuit part using the laminated body and the film The present invention provides a laminate comprising an insulating layer having suppressed dusting properties, an insulating film comprising the insulating layer, and an electronic circuit component comprising a pattern of the insulating layer. The laminate has a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a ... 02/01/07 - 20070026677 - Method for plasma etching performance enhancement A method for etching features in a dielectric layer is provided. A mask is formed over the dielectric layer. A protective silicon-containing coating is formed on exposed surfaces of the mask. The features are etched through the mask and protective silicon-containing coating. The features may be partially etched before the ... 02/01/07 - 20070026676 - Via hole machining for microwave monolithic integrated circuits A method for forming a via in a sapphire substrate with a laser machining system that includes an ultrafast pulsed laser source. The sapphire substrate is provided. Pulses of laser light are substantially focused to a beam spot on the first surface of the sapphire substrate such that each focused ... 02/01/07 - 20070026675 - System and method for improving mesa width in a semiconductor device A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench ... 02/01/07 - 20070026674 - Method of protecting wafer front pattern and method of performing double-sided process A wafer comprising a front surface and a back surface is provided. The wafer further includes a front pattern on the front surface, the front pattern having a plurality of holes. A low-viscosity fluid is formed on the front surface and filled into the holes. Following that, a high-viscosity fluid ... 01/25/07 - 20070020938 - Semiconductor probe with resistive tip and method of fabricating the same, and information recording apparatus, information reproducing apparatus, and information measuring apparatus having the semiconductor probe Provided are a semiconductor probe having a resistive tip, a method of fabricating the semiconductor probe, and a method of recording and reproducing information using the semiconductor probe. The semiconductor probe includes a tip and a cantilever. The tip is doped with first impurities. The cantilever has an end portion ... 01/25/07 - 20070020937 - Etch chamber with dual frequency biasing sources and a single frequency plasma generating source A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma. ... 01/25/07 - 20070020936 - Methods of etching features into substrates The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the ... 01/25/07 - 20070020935 - Process for enhancing solubility and reaction rates in supercritical fluids Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, ... 01/25/07 - 20070020934 - Hard mask structure for patterning of materials Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a ... 01/25/07 - 20070020933 - Method of cleaning treatment and method for manufacturing semiconductor device In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate. ... 01/18/07 - 20070015363 - Electronic board and manufacturing method thereof, electro-optical device, and electronic apparatus An electronic board includes: a substrate; and a wiring pattern provided on the substrate and having a part that forms a resistance element, the part having wiring specifications that are different from those of other parts. ... 01/18/07 - 20070015362 - Semiconductor device having storage nodes and its method of fabrication Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an ... 01/18/07 - 20070015361 - Manufacturing method of micro-electro-mechanical device A method of forming a microstructure body and a semiconductor element for controlling the microstructure body over the same substrate to reduce manufacturing cost, for mass-production of micromachines having a microstructure. In manufacturing a micromachine, a sacrifice layer is formed using a mask material for forming a pattern of a ... 01/11/07 - 20070010096 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: loading a wafer into a chamber including a ceramic dome coated with a material having etch tolerance against a plasma; etching a gate structure formed on the wafer, thereby generating etch remnants; and removing the etch remnants by ... 01/11/07 - 20070010095 - Surface treatment method using ion beam and surface treating device The problems to be solved by the present invention are to provide a novel surface treatment method and a surface treatment apparatus for surface cleaning or surface processing of a solid material, which utilize material that assumes a liquid state at normal temperature and pressure, and the surface treatment method ... 01/04/07 - 20070004208 - Plasma etching apparatus and plasma etching method The plasma processing apparatus is provided with a chamber comprising a dielectric wall at the position opposing an object to be processed. A flat coil arranged exterior of the dielectric wall creates an induction magnetic field for generating the plasma. A plate-shaped electrode capable of functioning as a Faraday shield ... 01/04/07 - 20070004207 - Full backside etching for pressure sensing silicon The formation of a semiconductor sensing device is disclosed, where the device can be used to sense pressure, for example. The device is formed by etching the entire backside of a semiconductor substrate or wafer. This streamlines the fabrication process by omitting a number of steps that would otherwise be ... 12/28/06 - 20060292876 - Plasma etching method and apparatus, control program and computer-readable storage medium In a method for plasma etching a wafer laminated with a target layer, a lower organic layer, an intermediate layer and an upper resist layer in that order from bottom, the method includes following steps: patterning the upper resist layer by exposure and development, plasma etching the intermediate layer by ... 12/21/06 - 20060286805 - Planarization process for pre-damascene structure including metal hard mask A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP ... 12/21/06 - 20060286804 - Method for forming patterned material layer A method for forming a patterned material layer comprises the following steps. First, a material layer is formed on a substrate, and then a patterned positive photoresist layer is formed on the material layer. Next, the material layer is etched by using the patterned positive photoresist layer as a mask. ... 12/14/06 - 20060281315 - Process of manufacture of ultra thin semiconductor wafers with bonded conductive hard carrier A process is described to enable the manufacture of a thinned (<50 μm semiconductor die) which can employ the use of standard equipment for the manufacture of the wafer and the packaging of the die singulated from the wafer. A standard thickness wafer (350 μm) first has junctions formed in ... 12/14/06 - 20060281314 - Wafer holder and method of holding a wafer A wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter of a wafer loaded on the wafer stage, the wafer stage outer-ring has an inner diameter at the upper side of the outer-ring ... 12/14/06 - 20060281313 - Etching method and method for forming contact opening An etching method is described, including a first etching step and a second etching step. The temperature of the second etching step is higher than that of the first etching step, such that the after-etching-inspection (AEI) critical dimension is smaller than the after-development-inspection (ADI) critical dimension. ... 12/14/06 - 20060281312 - Hydrogen and oxygen based photoresist removal process The present invention provides a photoresist removal process and a method for manufacturing an interconnect using the same. One embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a photoresist layer located thereover, and removing the photoresist layer using a plasma ... 12/07/06 - 20060276040 - Ion implanted microscale and nanoscale device method A method is used for producing nanoscale and microscale devices in a variety of materials, such as silicon dioxide patterned buried films. The method is inexpensive and reliable for making small scale mechanical, optical, or electrical devices and relies upon the implantation of ions into a substrate and subsequent annealing ... 12/07/06 - 20060276039 - Neck height equalization in magnetic write pole mold An improved mold, for use in the formation of a perpendicular magnetic write head, is described, together with a process for its manufacture. Conventional alumina is replaced by tantalum in the yoke portion of the mold. When both the tantalum and the alumina areas are simultaneously subjected to reactive ion ... 12/07/06 - 20060276038 - Thermal desorption of oxide from surfaces Disclosed is a method for removing a layer of native oxide from a surface of a substrate without altering the smoothness of the substrate surface comprising: 1) depositing on the substrate surface a thin sacrificial layer of the substrate surface material, having a thickness sufficient to react with all of ... 11/30/06 - 20060270230 - Critical dimension control for integrated circuits Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma is used to etch an amorphous carbon hard mask layer. The features of a pattern can be shrunk using a plasma etch to reduce the resist elements ... 11/30/06 - 20060270229 - Anodized aluminum oxide nanoporous template and associated method of fabrication In some embodiments, the present invention is directed to nanoporous anodized aluminum oxide templates of high uniformity and methods for making same, wherein such templates lack a AAO barrier layer. In some or other embodiments, the present invention is directed to methods of electrodepositing nanorods in the nanopores of these ... 11/23/06 - 20060264050 - Method and apparatus for chemical mixing in a single wafer process A method of and apparatus for mixing chemicals in a single wafer process. According to the present invention a chemical is fed into a valve system having a tube of a known volume. The chemical is fed into the valve system to fill the tube with a chemical to generate ... 11/23/06 - 20060264049 - Spin-printing of etchants and modifiers The present invention is directed to processes for printing compositions containing etchants or modifiers onto surfaces by spinning a filament from a viscoelastic polymer solution containing an etchant or modifier. The present invention also relates to viscoelastic compositions used in the printing processes, and devices made therefrom. ... 11/16/06 - 20060258158 - Polish method for semiconductor device planarization A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using ... 11/09/06 - 20060252265 - Etching high-kappa dielectric materials with good high-kappa foot control and silicon recess control An apparatus and a method for etching high dielectric constant (high-κ) materials using halogen containing gas and reducing gas chemistries are provided. One embodiment of the method is accomplished by etching a layer using two etch gas chemistries in separate steps. The first etch gas chemistry contain no oxygen containing ... 11/02/06 - 20060246722 - Etching technique for the fabrication of thin (ai, in, ga)n layers An etching technique for the fabrication of thin (Al, In, Ga)N layers. A suitable template or substrate is selected and implanted with foreign ions over a desired area to create ion implanted material. A regrowth of a device structure is then performed on the implanted template or substrate. The top ... 10/26/06 - 20060240671 - Method of reducing outgassing pollution A method for reducing outgassing pollution in a semiconductor process includes matching a pressure of a VCE with a pressure of a process chamber before reaction gas is injected into the process chamber, injecting the reaction gas into the process chamber, opening a partitioning door disposed between the VCE and ... 10/26/06 - 20060240670 - Etching of algainassb The present invention relates to a wet acid etchant for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0<x<1, 0<y<1, 0≦z<1 and 0<x+z<1, a process for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0<x<1, 0<y<1, 0≦z<1 and 0<x+z<1, and a semiconductor structure prepared by wet ... 10/19/06 - 20060234506 - Processing method for protection of backside of a wafer A temporal protecting layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protecting layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. In concerning with low cost and easily forming and removing, an oxide layer ... 10/12/06 - 20060228891 - Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface microwave plasma generating apparatus, semiconductor substrate etching apparatus, semiconductor substrate deposition apparatus, and microwave plasma g In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The antennas have respective pluralities of microwave transmissive openings formed therethrough. At least some of the openings of the respective antennas overlap with at least some of the openings ... 10/12/06 - 20060228890 - Cleaning solution and method of forming a metal pattern for a semiconductor device using the same A cleaning solution includes acetic acid, an inorganic acid, a fluoride compound, and deionized water, and may further include a corrosion inhibitor, a chelating agent, or a combination thereof. The cleaning solution may be used in the formation of a metal pattern in which a metal film including ruthenium is ... 10/12/06 - 20060228889 - Methods of removing resist from substrates in resist stripping chambers Methods for stripping resist from a semiconductor substrate in a resist stripping chamber are provided. The methods include producing a remote plasma containing reactive species and cooling the reactive species inside the chamber prior to removing the resist with the reactive species. The reactive species can be cooled by being ... 10/05/06 - 20060223318 - Semiconductor device manufacturing method for preventing patterns from inclining in drying process A method of manufacturing a semiconductor device of the present invention has the steps of forming a pattern made of a processed film or a resist on a substrate, washing the pattern with a washing liquid which is a liquid including at least water, spreading an amphophilic material that has ... 10/05/06 - 20060223317 - Plasma processing method and plasma processing apparatus The plasma processing method comprises the step of removing an organic material film forming an upper layer relative to a patterned SiOCH series film by the processing with a plasma of a process gas containing an O2 gas, wherein the plasma has an O2+ ion density not lower than 1×1011 ... 10/05/06 - 20060223316 - Surface treatment method, circuit lines formation method, circuit lines formation apparatus, and printed circuit board formed thereby The present invention relates to a method of surface treatment, a method for forming circuit lines, a printed circuit board formed thereby, and an apparatus for forming circuit lines on a substrate, wherein fine circuit lines are formed simply, rapidly, and economically. The method for forming circuit lines of the ... 10/05/06 - 20060223315 - Thermal oxidation of silicon using ozone A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other ... 10/05/06 - 20060223314 - Method of treating a composite spin-on glass/anti-reflective material prior to cleaning Methods are provided for cleaning a microelectronic device, and one method includes providing a substrate having a patterned SOG/anti-reflective material; performing a process to cure the patterned SOG/anti-reflective material; and performing a cleaning process to remove the cured SOG/anti-reflective material. An apparatus for cleaning a microelectronic device is provided that ... 09/21/06 - 20060211248 - Purifier for chemical reactor A method for purifying a gas stream in a semiconductor process system comprises cooling impurities in the gas stream. The gas stream may comprise an HCl gas having a moisture content. The moisture contacts a cold element onto which the moisture can condense. ... 09/14/06 - 20060205216 - Etching method and apparatus An etching method, for selectively etching a silicon nitride film to a silicon oxide film by using a processing gas in a processing chamber including an electrode therein, includes the steps of mounting a target object having the silicon oxide film and the silicon nitride film onto the electrode and ... 09/07/06 - 20060199388 - System and method for manufacturing semiconductor devices using a vacuum chamber The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to semiconductor manufacturing using a vacuum chamber. In one example, a method for semiconductor manufacturing includes: providing a photoresist layer for a wafer; removing solvent residues from the photoresist layer by using a vacuum chamber; and ... 08/31/06 - 20060194436 - Semiconductor device including resistor and method of fabricating the same In a semiconductor device including a resistor and a method of fabricating the same, the semiconductor device includes an isolation insulating layer disposed in a semiconductor substrate to define at least two active regions spaced from each other. A well resistor pattern is disposed below the isolation insulating layer to ... 08/31/06 - 20060194435 - Method of processing substrate, and method of and program for manufacturing electronic device A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate ... 08/24/06 - 20060189136 - Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. ... 08/17/06 - 20060183331 - Methods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substrates The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The ... 08/17/06 - 20060183330 - Laser assisted chemical etching method for release of microscale and nanoscale devices A method using an etchant and a laser for localized precise heating enables precise etching and release of MEMS devices with improved process control while expanding the number of materials used to make MEMS, including silicon-dioxide patterned films buried in and subsequently released from bulk silicon, as a direct write ... 08/17/06 - 20060183329 - Apparatus and method for reducing impurities in a semiconductor material An apparatus and method of treating multiple wafers to reduce the density of impurities as well as to improve the uniformity of substrate electrical characteristics without any thermal stress. The wafers are chemically treated, and heat treated in a sealed reaction tube under arsenic overpressure with a controlled thermal profile ... 08/03/06 - 20060172538 - Wet etching the edge and bevel of a silicon wafer A method and apparatus to selectively etch layers of various materials from the edge and bevel areas of the active side of a silicon wafer, as well as from the inactive side of a wafer are disclosed. The width of the etched edge generally varies from about 0.5 to about ... 07/13/06 - 20060154484 - Method of removing a low-k layer and method of recycling a wafer using the same In one embodiment, a method of removing a low-k layer at a low cost and a method of recycling a wafer using the same, is described. A fluoride treatment is performed on the low-k layer formed on an object using an aqueous hydrogen fluoride solution, and the low-k layer is ... 07/06/06 - 20060148257 - Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the ... 07/06/06 - 20060148256 - Method for forming patterns aligned on either side of a thin film etching the second pattern layer (18) in order to form the second pattern (22). ... 06/29/06 - 20060141789 - Method for etching and for forming a contact hole using thereof A method for forming a structure formed by etching which is typified by a contact hole in the semiconductor and a method for manufacturing a display device using the structure. The etching method includes at least, forming an organic mask having a first opening portion and a second opening portion ... 06/29/06 - 20060141788 - Method for fabricating semiconductor device capable of preventing scratch Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed; ... 06/29/06 - 20060141787 - Cleaning methods for silicon electrode assembly surface contamination removal Silicon electrode assembly decontamination cleaning methods and solutions, which control or eliminate possible chemical attacks of electrode assembly bonding materials, comprise ammonium fluoride, hydrogen peroxide, acetic acid, optionally ammonium acetate, and deionized water. ... 06/29/06 - 20060141786 - Method of manufacturing an electronic device and electronic device A method of manufacturing an electronic device, particularly an acceleration sensor, comprising providing a wafer (10) having first and second semiconductor layers (12, 16) with a buried oxide layer (14) therebetween and forming a semiconductor device (such as a detection circuit) on one side of the wafer (10) in the ... 06/22/06 - 20060134914 - Flexible circuits and method of making same Disclosed is a method for making flexible circuits in which portions of a tie layer are removed by etching the underlying polymer. Also disclosed are flexible circuits made by this method. ... 06/15/06 - 20060128151 - Method for removing photoresist layer and method for forming metal line in semiconductor device using the same Disclosed are a method for removing a photoresist layer and a method for forming a metal line using the same. The method for removing a photoresist pattern, including the steps of: forming a bottom layer on a substrate by using the photoresist pattern as a mask; and removing the photoresist ... 06/08/06 - 20060121736 - Semiconductor device and manufacturing method thereof An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region ... 06/08/06 - 20060121735 - Method for producing insulation structures The invention relates to processes for the formation of isolation structures for micro-machined sensors in single-crystal surface technology. In known processes, silicon structures defined by deep trenches are etched and uncovered by a “release etch” step also at their bottom surface towards the substrate. The subsequent lining of these trenches ... 05/18/06 - 20060105571 - Pneumatic method and apparatus for nano imprint lithography A method (and apparatus) for nano lithography, includes applying a pneumatic pressure to at least one of a surface of a semi-rigid mask or template and a portion of a surface of a resist-coated workpiece, and, by the applying of the pneumatic pressure, transferring a pattern from the mask to ... 05/11/06 - 20060099811 - Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate A method for structuring of silicon substrates for microsystem technological device elements, wherein the silicon substrate is covered with an etching mask and wherein the structures are furnished with a predetermined etching profile in the micrometer region with side walls and an etching depth At. For the generation of a ... 05/11/06 - 20060099810 - Laser micromachining method A laser micromachining method is disclosed wherein a workpiece is milled using an incident beam from a laser beam focused above the surface of the workpiece. The incident beam is guided by a plasma channel generated by the incident beam. The plasma channel, which has a relatively constant diameter over ... 05/04/06 - 20060094241 - Etchant for conductive materials and method of manufacturing a thin film transistor array panel using the same The present invention provides a method for manufacturing a thin film transistor (TFT) array panel by forming a gate line having a gate electrode on an insulating substrate; sequentially depositing a gate insulating layer and a semiconductor layer on the gate line; forming a drain electrode and a data line ... 04/27/06 - 20060088999 - Methods and compositions for chemical mechanical polishing substrates Methods and compositions are provided for planarizing a substrate surface with reduced or minimal defects in surface topography. In one aspect, a method is provided for processing a substrate comprising a dielectric material and polysilicon material disposed thereon, polishing the polysilicon material with a high topography selective polishing composition, and ... 04/20/06 - 20060084269 - Apparatus for generating gas plasma, gas composition for generating plasma and method for manufacturing semiconductor device using the same A method for manufacturing a semiconductor device may include: forming a main magnetic field having an axis, and forming a subsidiary magnetic field substantially parallel to the axis; applying an alternating current along a path between the main and the subsidiary magnetic fields; allowing a gas to flow along a ... 04/20/06 - 20060084268 - Method for production of charge-trapping memory cells An oxide layer, a nitride layer, and a layer of amorphous silicon are applied to a surface of a semiconductor substrate. A resist mask is applied and implantations are performed to form doped regions of source and drain and doped regions within the amorphous silicon layer. The resist mask and ... 04/13/06 - 20060079091 - Mask, method of producing the same, and method of producing semiconductor device To provide a mask able to reduce the thickness of a membrane and maintain the mask strength and a method of producing a semiconductor device able to form a fine pattern with a high accuracy and a method of producing the mask. A mask comprising a thin film, holes formed ... 04/06/06 - 20060073703 - Dynamic edge bead removal A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second ... 03/30/06 - 20060068591 - Fabrication of channel wraparound gate structure for field-effect transistor A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is ... 03/30/06 - 20060068590 - Metal gate transistors with epitaxial source and drain regions An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor. ... 03/30/06 - 20060068589 - Selective barrier slurry for chemical mechanical polishing The polishing solution is useful for removing a barrier from a semiconductor substrate. The solution contains by weight percent 0.001 to 25 oxidizer, 0.0001 to 5 anionic surfactant, 0 to 15 inhibitor for a nonferrous metal, 0 to 40 abrasive, 0 to 20 complexing agent for the nonferrous metal, 0.01 ... 03/23/06 - 20060063384 - Mask patterns for semiconductor device fabrication and related methods and structures Methods of forming an integrated circuit device may include forming a resist pattern on a layer of an integrated circuit device with portions of the layer being exposed through openings of the resist pattern. An organic-inorganic hybrid siloxane network film may be formed on the resist pattern. Portions of the ... 03/23/06 - 20060063383 - Cmp process endpoint detection method by monitoring and analyzing vibration data An apparatus and method for monitoring vibration of a chemical-mechanical planarization (CMP) tool to detect CMP process endpoint. In one embodiment, the CMP tool includes a wafer carrier configured to directly or indirectly receive a semiconductor wafer. The carrier rotates the semiconductor wafer with respect to a polishing pad. It ... 03/23/06 - 20060063382 - Method to fabricate copper-cobalt interconnects A method to form copper-cobalt interconnects comprises rinsing a copper substrate with deionized water, heating a mild etchant solution and rinsing the copper substrate with the heated mild etchant solution, heating an electroless plating solution and rinsing the copper substrate with a portion of the heated electroless plating solution, heating ... 03/16/06 - 20060057849 - Apparatus and method for stripping silicon nitride An apparatus and a method for stripping silicon nitride are disclosed that facilitate automatic, real-time, and exact measurement of etch rate and an ending time of the etching process when silicon nitride is stripped with phosphoric acid solution. The method for stripping silicon nitride includes the steps of: a) measuring ... 03/16/06 - 20060057848 - Method for preparing a deep trench and an etching mixture for the same The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of ... 03/16/06 - 20060057847 - Resin forming mold and production method for the resin forming mold The present invention is to provide a resin-forming mold having high releasability and permitting a production without increasing production costs. The resin-forming mold can be used to produce a resin-molded product having minute uneven portions on a front face thereof, such as a surface light source device-use light guide for ... 03/16/06 - 20060057846 - Composition for use as sanitary earthenware material, method for production thereof, method for manufacturing sanitary earthenware using said composition Disclosed are a composition for a sanitary ware body for use in slip casting, possessing excellent long-term storage stability, transportability and slurry regeneration, a production process of the same, and a production process of a sanitary ware using the composition for a sanitary ware body. This composition for a sanitary ... 03/02/06 - 20060046489 - Semiconductor memory device and method for fabricating the same The present invention provides a semiconductor memory device capable of preventing bridge formations in a peripheral circuit region and improving a process margin and a method for fabricating the same. The semiconductor memory device includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality ... 03/02/06 - 20060046488 - Germanium-on-insulator fabrication utilizing wafer bonding Methods of forming a germanium on insulator structure and its associated structures are described. Those methods comprise forming an epitaxial germanium layer on a sacrificial silicon layer, removing a portion of the epitaxial germanium layer, activating the epitaxial germanium layer and an oxide layer disposed on a silicon substrate in ... 03/02/06 - 20060046487 - Method of manufacturing a semiconductor device, and a semiconductor substrate A method of manufacturing a semiconductor device. In the method, a thin film is formed on an Si substrate having face orientation (100), that part of the thin film, which lies on an element-isolating region, is removed. Then, the Si substrate is subjected to selective etching, making a trench in ... 03/02/06 - 20060046486 - Method of manufacturing microlens, microlens, microlens array, electro-optical device, and electronic apparatus A method of manufacturing a microlens includes: forming on a transparent substrate an etching stop layer in a lens formation region where a curved lens surface of the microlens is to be formed, the etching stop layer having an island shape as a planar shape thereof; forming an intermediate layer ... 03/02/06 - 20060046485 - Method of manufacturing package substrate with fine circuit pattern using anodic oxidation Disclosed herein is a method of manufacturing a package substrate with a fine circuit pattern using anodic oxidation. By anodizing a metal core which is opened through a masking process, oxidation layers are formed in open areas of the metal core to insulate portions of circuit pattern from each other. ... 03/02/06 - 20060046484 - Method for integrated circuit fabrication using pitch multiplication Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of ... 03/02/06 - 20060046483 - Critical dimension control for integrated circuits Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma is used to etch an amorphous carbon hard mask layer. The features of a pattern can be shrunk using a plasma etch to reduce the resist elements ... 03/02/06 - 20060046482 - Semiconductor processing using energized hydrogen gas and in combination with wet cleaning A method of fabricating a semiconductor device. The method comprises subjecting a substrate having formed thereon photoresist layer to a plasma hydrogen, the substrate further having formed thereon a sacrificial layer; contacting the photoresist layer with a photoresist removal solution; subjecting the sacrificial layer to a plasma hydrogen; and contacting ... 02/23/06 - 20060040500 - Nitride semiconductor chip and method for manufacturing nitride semiconductor chip A method for manufacturing a nitride semiconductor device in which nitride crystals are sequentially grown on a substrate such as sapphire by MOCVD or the like, and p electrode and n electrode are formed. The wafer is not cut along two perpendicular directions, but rather is cut along two directions ... 02/23/06 - 20060040499 - In situ surface contaminant removal for ion implanting Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating ... 02/09/06 - 20060030153 - Apparatus and method for manufacturing semiconductor device incorporating fuse elements An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for ... 02/09/06 - 20060030152 - Method of manufacturing substrate having recessed portions for microlenses and transmissive screen A method of manufacturing a substrate having recessed portions for microlenses, the substrate being provided with a plurality of recessed portions on a surface thereof and the microlenses being formed by supplying resin to each of the recessed portions, the method includes: forming an etching mask film; forming through holes ... 02/02/06 - 20060024966 - Manufacturing method of semiconductor device A manufacturing method of a semiconductor device having a through-hole electrode is offered to improve reliability and yield of the semiconductor device. A via hole penetrating through a semiconductor substrate is formed at a location corresponding to a pad electrode. An insulation film is formed on a back surface of ... 02/02/06 - 20060024965 - Method of etching cavities having different aspect ratios A method of etching cavities having different aspect ratios. An etching stop layer is formed on the bottom surface of a substrate, and a mask pattern is formed on the top surface of the substrate. The mask pattern includes a plurality of sacrificial patterns positioned on both a first cavity ... 01/26/06 - 20060019497 - Reduced feature-size memory devices and methods for fabricating the same This disclosure relates to systems and methods for reducing feature sizes. One of these methods enables formation of an original feature having a size in a length or width dimension of between about 100 and about 1000 nanometers with a system capable of patterning features to a minimum size of ... 12/29/05 - 20050287809 - Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming ... 12/29/05 - 20050287808 - Lactate-containing corrosion inhibitor The corrosion of aluminum-based metal films may be minimized by applying a lactate-containing solution to the aluminum-based metal films before the aluminum-based metal films are etched. The lactate-containing solution is applied to the aluminum-based metal film before the film is etched with a corrosive etchant. Minimizing the corrosion of the ... 12/22/05 - 20050282387 - Metal polish composition, polishing method using the composition and method for producing wafer using the polishing method wherein m represents an integer of from 1 to 3 and n represents an integer of from 0 to 2, with m and n being such that (3-n-m) is an integer of from 0 to 2; A represents a straight-chained or branched alkylene, phenylene or substituted phenylene group having 1 ... 12/08/05 - 20050272263 - Roll to roll manufacturing of organic solar modules The invention discloses for the first time how an organic component can be produced in a process designed entirely as a roll-to-roll process. The advantage of the continuous production method described here is, further, that the active regions of the active semiconductor layer are not exposed to unprotected solvents and/or ... 11/17/05 - 20050255701 - Methods of forming semiconductor constructions The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers ... 11/10/05 - 20050250330 - Method utilizing compensation features in semiconductor processing A photolithography and etch process sequence includes a photomask having a pattern with compensation features that alleviate patterning variations due to the proximity effect and depth of focus concerns during photolithography. The compensation features may be disposed near isolated or outermost lines of a device pattern. A photoresist pattern is ... 11/10/05 - 20050250329 - Compositions for chemical mechanical planarization of tantalum and tantalum nitride The present invention relates to compositions for the chemical mechanical planarization (“CMP”) of barrier/adhesion layers, particularly Ta/TaN barrier/adhesion layers as occur in the manufacture of integrated circuits. CMP compositions comprise an aqueous solution of oxidizer and colloidal silica abrasive. Oxidizers include hydroxylamine nitrate, nitric acid, benzotriazole, ammonium nitrate, aluminum nitrate, ... 11/03/05 - 20050245085 - Method for forming pattern using printing method A method for forming a pattern is provided that includes: providing a cliché having a plurality of convex patterns; applying an adhesive force reinforcing agent onto each surface of the convex patterns; forming an etching object layer on a substrate and then applying ink onto an upper portion of the ... 10/20/05 - 20050233588 - Semiconductor constructions The invention includes methods by which the size and shape of photoresist-containing masking compositions can be selectively controlled after development of the photoresist. For instance, photoresist features can be formed over a substrate utilizing a photolithographic process. Subsequently, at least some of the photoresist features can be exposed to actinic ... 10/20/05 - 20050233587 - Method for making an anisotropic conductive film pointed conductive inserts The method comprises the etching of at least one pattern (C1, K1) in a single crystal substrate (15) in order to form at least one cell (22, 26) with a bottom intended for drawing the contour of an end of an insert (23, 27). The drawing of the pattern is ... 10/06/05 - 20050221614 - Method and apparatus for forming contact hole A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film, including: etching the insulating film using reactive ion etching to a depth whereat ... 09/29/05 - 20050215058 - Methods of forming channels on an integrated circuit die and die cooling systems including such channels A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels. ... 09/29/05 - 20050215057 - Arsenic dopants for pulling of silicon single crystal, process for producing thereof and process for producing silicon single crystal using thereof Silicon single crystal is pulled by the Czochralski method, using an As dopant comprising a mixed sintered compact of arsenic and silicon, the molar ratio of silicon being not smaller than 35% and not greater than 55% relative to arsenic. ... 09/29/05 - 20050215056 - Bonded wafer processing method According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed. ... 09/22/05 - 20050208768 - Method for manufacturing gratings in semiconductor materials that readily oxidise The present invention is a combination of in-situ etching with a grating mask pattern comprised only of semiconductor material, together with the fabrication of a protective layer beneath the semiconductor grating mask that protects the semiconductor material that readily oxidises. As such the present invention is based on a two-stage ... 09/15/05 - 20050202675 - Calibration standard for critical dimension verification of sub-tenth micron integrated circuit technology A critical dimension control wafer for calibrating process control scanning electron microscopes is described. The test wafer provides one or more test structures each consisting of an array of parallel trenches precision micro-machined in a metal plate. The trenches are formed, preferably in an aluminum/copper alloy plate, using focused ion ... 09/08/05 - 20050196962 - Method for forming a self-aligned germanide and devices obtained thereof A method for removing unreacted metal from a germanium layer, a germanide layer and or a dielectric material. The method includes removing the unreacted metal using a chemical composition that includes one or more hydrohalides, such as in an aqueous form. In certain embodiments, the chemical composition may also include ... 09/01/05 - 20050191857 - Capping layer for a semiconductor device and a method of fabrication Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least ... 09/01/05 - 20050191856 - Method of forming high aspect ratio structures An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external ... 08/25/05 - 20050186798 - Process for manufacturing semiconductor devices and related semiconductor device A process for manufacturing semiconductor devices including a plurality of semiconductor layers arranged over a substrate, the semiconductor layers including at least one active layer. The process comprises the steps of vertically etching the plurality of semiconductor layers, the vertical etching including reactive ion etching of the semiconductor layers, and ... 08/25/05 - 20050186797 - Abs through aggressive stitching Aggressive (i.e. tight tolerance) stitching offers several advantages for magnetic write heads but at the cost of some losses during pole trimming. This problem has been overcome by replacing the alumina filler layer, that is used to protect the stitched pole during trimming, with a layer of electro-plated material. Because ... 08/18/05 - 20050181614 - Variable shape antenna etching system and antenna formed thereby An antenna formation device/method has been developed to create variable shaped antennas using predetermined interference patterns to expose and develop a photoresist layer that is etched on a substrate to form the structure corresponding to the desired variable shaped antenna. ... 08/18/05 - 20050181613 - Supercritical fluid-assisted deposition of materials on semiconductor substrates Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable ... 08/18/05 - 20050181612 - Chemical thinning of silicon body of an soi substrate The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning. ... 08/18/05 - 20050181611 - Method for preparing large-size substrate A large-size substrate having improved flatness is prepared by measuring the flatness of one surface or opposite surfaces of a large-size substrate having a diagonal length of at least 500 mm, and partially removing raised portions on the one surface or opposite surfaces of the substrate by means of a ... 08/18/05 - 20050181610 - Method of manufacturing a semiconductor device [Object] In performing an anisotropic etching process after a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, a portion that is not etched is left at an edge of a second conductive film to shorten an LDD region. It is an object to ... 08/18/05 - 20050181609 - Polishing fluid and polishing method A polishing slurry including an oxidant, a metal oxide dissolver, a metal inhibitor and water and having a pH from 2 to 5. The metal oxide dissolver contains one or more types selected from one or more acids (A-group) selected from acids of which the dissociation constant (pKa) of a ... 08/18/05 - 20050181608 - Method and apparatus for etching photomasks A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate ... 08/11/05 - 20050176249 - Controlled growth of gallium nitride nanostructures A transition metal substituted, amorphous mesoporous silica framework with a high degree of structural order and a narrow pore diameter distribution (±0.15 nm FWHM) was synthesized and used for the templated growth of GaN nanostructures, such as single wall nanotubes, nanopipes and nanowires. The physical properties of the GaN nanostructures ... 08/04/05 - 20050170653 - Semiconductor manufacturing method and apparatus A method of manufacturing a semiconductor device, comprising the steps of washing the surface of a substrate having insulation areas and metal areas exposed to the surface by using organic cleaning solvent, and radiating ultra-violet ray on the surface of the washed substrate, whereby the accumulation of a residue on ... 08/04/05 - 20050170652 - Method for manufacturing wiring substrate and method for manufacturing electronic device A method for manufacturing a wiring substrate includes the steps of (a) providing a first surface-active agent in first and second areas and of a substrate, (b) providing a second surface-active agent in the first area of the substrate, (c) providing a catalyst on the second surface-active agent, and (d) ... 08/04/05 - 20050170651 - Semiconductor manufacturing apparatus The wafer holder includes the heater 1 for carrying the semiconductor wafer thereon to heat the same, and the cooling block 2 for cooling the heater 1. The cooling block 2 is arranged so as to come into and out of abutment against the back 1b of the heater on ... 08/04/05 - 20050170650 - Electroless palladium nitrate activation prior to cobalt-alloy deposition In one embodiment, a method for activating a metal layer prior to depositing a cobalt-containing capping layer is provided which includes exposing the metal layer to an electroless activation solution to deposit a palladium layer on the metal layer and depositing the cobalt-containing capping layer on the palladium layer. The ... 08/04/05 - 20050170649 - Cdte single crystal and cdte polycrystal, and method for preparation thereof A CdTe single crystal, wherein chlorine concentration in the crystal is between 0.1 and 5.0 ppmwt and resistivity at room temperature is not less than 1.0×109 Ω·cm is obtained by growing the crystal according to one of a vertical gradient freezing method, a horizontal gradient freezing method, a vertical Bridgman ... 07/28/05 - 20050164508 - Method of electrolytic deposition of an intrinsically conductive polymer upon a non-conductive substrate A capacitor and method for manufacturing the capacitor. The capacitor comprises an anode; a dielectric oxide layer coated on the anode and a plurality of conductive islands coated on the dielectric oxide layer. An organic conductive cathode is coated on the dielectric layer and conductive islands. ... 07/28/05 - 20050164507 - Negative photoresist composition including non-crosslinking chemistry A negative photoresist composition and a method of patterning a substrate through use of the negative photoresist composition. The composition includes: a radiation sensitive acid generator; a hydroxy-containing additive; and a resist polymer derived from at least one first monomer. The resist polymer may be further derived from a second ... 07/28/05 - 20050164506 - Method and apparatus for backside polymer reduction in dry-etch process A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, ... 07/28/05 - 20050164505 - Land grid array membrane Embodiments of the invention provide a membrane for a land grid array (LGA) that reduces the likelihood and extent of deformation of the LGA contacts, as well as contamination thereof by foreign material. For one embodiment, the LGA has a number of holes formed therein that correspond to the LGA ... 07/28/05 - 20050164504 - Method for etching high aspect ratio features in iii-v based compounds for optoelectronic devices RIE etching of III-V semiconductors is performed using HBr or combinations of group VII gaseous species (Br, F, I) in a mixture with CH4 and H2 to etch high aspect ratio features for optoelectronic devices. ... 07/28/05 - 20050164503 - Method and structure for ultra narrow gate A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the ... 07/28/05 - 20050164502 - Immersion liquids for immersion lithography Compositions for immersion liquid materials and associated immersion lithography systems and techniques. Examples of polymer or oligomer-based immersion liquids are described to exhibit superior material properties for immersion lithography in comparison with water and some other commonly-used immersion liquids. In addition, certain material additives may be added to water and ... 07/28/05 - 20050164501 - Process for making photonic crystal circuits using an electron beam and ultraviolet lithography combination A process for making photonic crystal circuit and a photonic crystal circuit consisting of regularly-distributed holes in a high index dielectric material, and controllably-placed defects within this lattice, creating waveguides, cavities, etc. for photonic devices. The process is based upon the discovery that some positive ultraviolet (UV) photoresists are electron ... 07/21/05 - 20050159002 - Sputtered spring films with low stress anisotropy Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material compositions. In one embodiment, isotropic internal stress is achieved by manipulating the fabrication ... 07/21/05 - 20050159001 - Insulating film composition having improved mechanical property An insulating film forming composition having good mechanical and insulating properties comprises a silica sol having a good dispersion stability, an organic siloxane polymer and a hydrophobic organic solvent, wherein the silica sol has primary-particles having an average particle size of 5 to 15 nm and secondary-particles having an average ... 07/21/05 - 20050159000 - Method for fabricating nitride-based compound semiconductor element A method for fabricating a nitride semiconductor element according to the present invention comprises the steps of: forming a nitride semiconductor layer 13 on a base substrate 11; forming, on part of the upper surface of the nitride semiconductor layer 13, a conductive film 14 made of an electron emitting ... 07/14/05 - 20050153553 - Etching method In this etching method, since an etching gas is introduced before introduction of free radicals into a processing chamber, the etching gas has been adsorbed on the surface of substrates when the free radicals are introduced. Accordingly, the free radicals react with the etching gas adsorbed on the surface of ... 07/14/05 - 20050153552 - Crystallization apparatus and method, manufacturing method of electronic device, electronic device, and optical modulation element A manufacturing method of an electronic device includes positioning a processed substrate with respect to a substrate stage of a crystallization apparatus and supporting it with at least one positioning mark previously provided on the processed substrate being used as a references, applying a modulated light beam to a predetermined ... 07/14/05 - 20050153551 - Methods for deposition of semiconductor material The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from ... 07/14/05 - 20050153550 - Process for producing silicon single crystal layer and silicon single crystal layer A thermal processing operation is performed for a silicon wafer W (silicon single-crystal layer) in an atmosphere gas which is formed by a hydrogen gas or an inert gas or a mixture gas of these gases at a temperature in a range of 600° C. to 950° C. (here, the ... 07/07/05 - 20050148181 - Method for producing a silicon wafer Provided is a method for producing a silicon wafer those surfaces exhibit precise flatness and minute surface roughness, and which allows one to visually discriminate between the front and rear surfaces, the method comprising a slicing step of slicing a single-crystal ingot into thin disc-like wafers, a chamfering step of ... 07/07/05 - 20050148180 - Photoresist process to enable sloped passivation bondpad openings for ease of metal step coverings The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The ... 07/07/05 - 20050148179 - Organic semiconductor composition, organic semiconductor element, and process for producing the same Disclosed is an organic semiconductor composition containing particles and an organic semiconducting compound combining with the particles. ... 07/07/05 - 20050148178 - Method for fabricating a p-channel field-effect transistor on a semiconductor substrate A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form ... 06/30/05 - 20050142880 - Polymer removal method for use in manufacturing semiconductor devices Polymer removal methods for use in manufacturing semiconductor devices are disclosed. An example polymer removal method places wafers on which metal patterns are formed on a wet station employing a batch spin method. The example method treats the wafers with a chemical while rotating the wafers at a first speed ... 06/30/05 - 20050142879 - Wafer bonded epitaxial templates for silicon heterostructures A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The ... 06/30/05 - 20050142878 - Method for detecting end-point of chemical mechanical polishing process Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. ... 06/30/05 - 20050142877 - Chemical-mechanical polishing proximity correction method and correction pattern thereof A chemical-mechanical polishing (CMP) proximity correction method for polishing a wafer is provided. The wafer has a polish area and a protected area. The method includes forming a material layer over the wafer to cover the polish area and the protected area and then forming a protective layer over the ... 06/23/05 - 20050136668 - Mask, method for manufacturing a mask, method for manufacturing an organic electroluminescence device, organic electroluminescence device, and electronic apparatus A mask is provided including a plurality of through-holes penetrating a silicon substrate with (100) orientation. The walls defining the through-holes include a vertical part and an inclined part. The vertical part extends in a vertical direction relative to a principal plane of the substrate, and the inclined part extends ... 06/23/05 - 20050136667 - Superabrasive particle synthesis with controlled placement of crystalline seeds An improved method for synthesizing superabrasive particles provides high quality industrial superabrasive I-,articles with high yield and a narrow size distribution. The synthesis method includes forming a substantially homogeneous mixture of raw material and catalyst material or layers of raw material and metal catalyst. A plurality of crystalline seeds is ... 06/23/05 - 20050136666 - Method and apparatus for etching an organic layer A method and system for etching an organic layer on a substrate in a plasma processing system comprising: introducing a process gas comprising NxOy, wherein x, y represent integers greater than or equal to unity. Additionally, the process chemistry can further comprise the addition of an inert gas, such as ... 06/23/05 - 20050136665 - Method of forming an insulator between features of a semiconductor device A method of forming an insulator between features of a semiconductor device. An insulating material such as high-density plasma (HDP) oxide is deposited over and between features formed on a semiconductor device. The height of the insulating material between the features is preferably less than the height of the features. ... 06/23/05 - 20050136664 - Novel process for improved hot carrier injection A method for fabricating aluminum bonding pads is described. A passivation layer is provided overlying semiconductor device structures in and on a substrate. A bonding pad layer is deposited overlying the passivation layer and within openings in the passivation layer to underlying semiconductor device structures. A masking layer is formed ... 06/23/05 - 20050136663 - Single-crystal-silicon 3d micromirror In a 3D free space micromirror device, a mirror plate is joined with actuators through flexible springs where the other ends of the actuators have fixed support on the substrate. Single crystal silicon and aluminum are used as bi-morph materials with silicon dioxide providing electrical isolation between the two. Thickness ... 06/23/05 - 20050136662 - Method to remove fluorine residue from bond pads The process of the present invention comprises reactive ion etching of AlxFyOz oxide deposits on aluminum-containing bond pads using feed gases, such as, SF6/CF4/Ar or Cl2/BCL3/Ar. whose active plasma etches the AlxFyOz oxide deposits by physical etching and chemical etching for more complete removal of the AlxFyOz oxide deposits. ... 06/16/05 - 20050130427 - Method of forming thin film for improved productivity There is provided a method of forming a thin film for providing improved fabrication productivity. The method includes introducing a semiconductor substrate into a process chamber. A process thin film is formed on the semiconductor substrate, in which a chamber coating layer is formed on inner walls of the process ... 06/16/05 - 20050130426 - Processing method for glass substrate, processed glass product and stress applying apparatus A processing method for glass substrate of the present invention includes: applying heat and external force to a glass substrate and then cooling it down to thereby form a compression stressed part having a different etching rate from that of other parts with respect to an etching reagent to be ... 06/16/05 - 20050130425 - Method of manufacturing rfid There is a method of manufacturing an RFID, in which a semiconductor chip with a memory is bonded to an antenna, so that the information recorded in the memory can be transmitted through the antenna. In the RFID, a PET film, a PEN film, or a sheet of paper is ... 06/16/05 - 20050130424 - Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an ... 06/16/05 - 20050130423 - Method for forming inductor in semiconductor device The present invention relates to a method for forming an inductor in a semiconductor device. The method comprises the steps of forming a first metal layer on a semiconductor substrate in which a predetermined structure is formed, and then patterning the first metal layer so that a predetermined region of ... 06/16/05 - 20050130422 - Method for patterning films A process for patterning films comprises the steps of (a) vapor depositing resist material onto a film disposed on a substrate through a repositionable aperture mask, and (b) using a subtractive process to remove the exposed portion of the film. ... 06/16/05 - 20050130421 - Method for removing a resist mask with high selectivity to a carbon hard mask used for semiconductor structuring The present invention relates to a method for removing a resist selective to a carbon hard mask including providing an etching plasma comprising of at least hydrogen at a predetermined temperature level and a predetermined pressure level in a reaction chamber, and etching the resist selectively to the mask with ... 06/16/05 - 20050130420 - Cleaning method using ozone di process A semiconductor cleaning method, including providing a semiconductor wafer, forming a first layer of oxide over the semiconductor wafer, forming a floating gate layer over the first layer of oxide, forming a second layer of oxide over the floating gate layer, etching the first layer of oxide, the floating gate ... 06/09/05 - 20050124164 - Fine particle film forming apparatus and method and semiconductor device and manufacturing method for the same After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 μm or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through ... 06/09/05 - 20050124163 - Dynamic random access memory circuitry comprising insulative collars A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive ... 06/09/05 - 20050124162 - Fabrication method for a hard mask on a semiconductor structure The present invention provides a fabrication method for a for a hard mask on semiconductor structure having the following steps: provision of a semiconductor substrate (1); application of a hard mask layer (5) to the semiconductor substrate (1); application of a silicon-containing spin-on mask layer (13) on the hard mask ... 06/09/05 - 20050124161 - Growth and integration of epitaxial gallium nitride films with silicon-based devices Epitaxial gallium nitride is grown on a silicon substrate while reducing or suppressing the formation of a buffer layer. The gallium nitride may be grown directly on the silicon substrate, for example using domain epitaxy. Alternatively, less than one complete monolayer of silicon nitride may be formed between the silicon ... 06/09/05 - 20050124160 - Novel multi-gate formation procedure for gate oxide quality improvement A process for forming a semiconductor device with multiple gate insulator thicknesses, wherein exposed surfaces of a semiconductor substrate are protected during a photoresist stripping procedure, has been developed. After growth of an insulator layer on the entire surface of a semiconductor substrate portions of the insulator layer not covered ... 06/09/05 - 20050124159 - Deflectable microstructure and method of manufacturing the same through bonding of wafers A method of making a deflectable, free hanging micro structure having at least one hinge member, the method includes the steps of providing a first sacrificial wafer having a single crystalline material constituting material forming the micro structure. A second semiconductor wafer including necessary components for forming the structure in ... 06/02/05 - 20050118819 - Post-cmp treating liquid and method for manufacturing semiconductor device There is disclosed a post-CMP treating liquid comprising water, and resin particles dispersed in the water and having a functional group at a surface thereof, or comprising water, resin particles dispersed in the water, and an additive having a functional group and incorporated in the water. The post-CMP treating liquid ... 06/02/05 - 20050118818 - Etching method, method of manufacturing semiconductor device, and semiconductor device In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of ... 06/02/05 - 20050118817 - Resist pattern forming method, magnetic recording medium manufacturing method and magnetic head manufacturing method A mold having a pattern of a concavo-convex surface including protrusion and recess is prepared and the pattern is transferred to a resist layer formed on a substrate by an imprinting method. The side surface of a protrusion of the transferred resist pattern is then etched so that the protrusion ... 06/02/05 - 20050118816 - Method for fabricating a semiconductor component A method for fabricating a semiconductor power component is disclosed. In one embodiment, the method for fabricating a semiconductor power component includes formation of a semiconductor structure in/on a substrate, a semiconductor region serving as a stop layer being formed at the level of a target thickness of the semiconductor ... 06/02/05 - 20050118815 - Method of manufacturing optical semiconductor integrated circuit device In an existing optical semiconductor integrated circuit device, a silicon nitride film that is an anti-reflection film is used as an etching stopper film at the etching of an insulating film and by means of wet etching the insulating film is removed once for all. Accordingly, there is a problem ... 06/02/05 - 20050118814 - Method for depositing silicon nitride layer of semiconductor device Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the ... 06/02/05 - 20050118813 - Removal of mems sacrificial layers using supercritical fluid/chemical formulations A method and composition for removing silicon-containing sacrificial layers from Micro Electro Mechanical System (MEMS) and other semiconductor substrates having such sacrificial layers is described. The etching compositions include a supercritical fluid (SCF), an etchant species, a co-solvent, and optionally a surfactant. Such etching compositions overcome the intrinsic deficiency of ... 06/02/05 - 20050118812 - Method of detecting, identifying and correcting process performance A method for material processing utilizing a material processing system (1) to perform a process. The method a process, measures a scan of data, and transforms the data scan into a signature including at least one spatial component. The scan of data can include a process performance parameter (14) such ... ### FreshPatents.com Support - Terms & Conditions |