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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Copper Of Copper Alloy Conductor Copper Of Copper Alloy ConductorCopper Of Copper Alloy Conductor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087567 - Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior ... 04/12/07 - 20070082488 - Semiconductor device and manufacturing method thereof A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on ... 04/12/07 - 20070082487 - Methods for discretized processing of regions of a substrate The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is ... 04/05/07 - 20070077762 - Method of accelerating test of semiconductor device Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings ... 04/05/07 - 20070077761 - Technique for forming a copper-based metallization layer including a conductive capping layer By providing a conductive capping layer for metal-based interconnect lines, an enhanced performance with respect to electromigration may be achieved. Moreover, a corresponding manufacturing technique is provided in which via openings may be reliably etched into the capping layer without exposing the underlying metal, such as copper-based material, thereby also ... 03/29/07 - 20070072420 - Method of forming copper interconnection using dual damascene process and semiconductor device having copper interconnection according to the same Disclosed is a method of forming a copper interconnection using a dual damascene process, in which an etch profile anomaly and the trench depth variation caused by the trench etching process are reduced or prevented, so that the copper interconnection is obtained substantially without voids or interconnection defects. The method ... 03/08/07 - 20070054489 - Interconnect structures with encasing cap and methods of making thereof A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure. ... 03/08/07 - 20070054488 - Low resistance and reliable copper interconnects by variable doping A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a ... 03/01/07 - 20070049027 - Chemical mechanical polishing and method for manufacturing semiconductor device using the same Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or more layers are measured. A barrier metal layer and a metal layer are sequentially ... 03/01/07 - 20070049026 - Dielectric film and process for its fabrication A dielectric film production process comprising a baking step in which a dielectric film is formed by heating a precursor layer formed on a metal layer, wherein the metal layer contains at least one type of metal selected from the group consisting of Cu, Ni, Al, stainless steel and inconel, ... 03/01/07 - 20070049025 - Chemical-mechanical planarization composition having ketooxime compounds and associated method for use A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition contains a ketooxime compound and water. The composition may also contain an abrasive and/or a per compound oxidizing agent. The composition affords tunability of removal rates for metal, barrier material, and dielectric layer materials ... 03/01/07 - 20070049024 - Manufacture method for semiconductor device having concave portions filled with conductor containing cu as its main composition An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing ... 02/15/07 - 20070037394 - A method for using a cu beol process to fabricate an integrated circuit (ic) originally having an al design A semiconductor fabrication method or process is provided for fabricating an integrated circuit (IC) originally having an Al backend design using a Cu BEOL fabrication process. The method converts the Al backend design to a Cu backend design without redesigning the IC for Cu BEOL fabrication process, and uses the ... 02/08/07 - 20070032080 - System and method for manufacturing flexible copper clad laminate film Disclosed is a system and a method for manufacturing flexible copper clad laminate film capable of efficiently electroplating both surfaces of a polyimide-based film to form copper plating layers thereon while making it easy to repair and maintain the apparatus or clean its plating or cleaning bath. The system includes ... 01/25/07 - 20070020932 - Manufacturing method of wiring board and semiconductor device A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method ... 01/25/07 - 20070020931 - Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy and semiconductor device of this kind (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy ... 01/04/07 - 20070004206 - Improved hdp-based ild capping layer A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound ... 12/28/06 - 20060292875 - Method for enhancing electrode surface area in dram cell capacitors Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, ... 11/30/06 - 20060270228 - Method of forming metal pattern using selective electroplating process A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the ... 11/30/06 - 20060270227 - Hillock reduction in copper films A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing) or other methods. The citric acid treatment may take place during a cleaning operation that takes place in a ... 11/23/06 - 20060264048 - Interconnect structure diffusion barrier with high nitrogen content In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm. ... 10/05/06 - 20060223313 - Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same A semiconductor chip comprising at least one contact area for electrically connecting the chip to a substrate, the contact area comprising a metallic contact pad covered by a seed layer and at least one copper interconnect post having a base surface directly contacting the contact area and extending from the ... 09/07/06 - 20060199387 - Local multilayered metallization An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a function of the width. In an alternate embodiment, a metallization structure having ... 09/07/06 - 20060199386 - Semiconductor device with low-resistance inlaid copper/barrier interconnects and method for manufacturing the same An inlaid copper/barrier interconnect includes a semiconductor substrate; a carbon-doped oxide (CDO) dielectric layer disposed over the semiconductor substrate; a damascene recess etched into the CDO dielectric layer; an alpha-phase tantalum (α-Ta) single-layer barrier sputter deposited on sidewall and bottom of the damascene recess; and a conductive layer deposited directly ... 08/24/06 - 20060189135 - Trench interconnect structure and formation method Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I2R losses, and defects or variations due to cusping. Embodiments of the methods involve forming an opening in an insulating layer, where the opening forms a ... 08/24/06 - 20060189134 - Ta-tan selective removal process for integrated device fabrication Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the ... 08/24/06 - 20060189133 - Reliable beol integration process with direct cmp of porous sicoh dielectric The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of ... 08/17/06 - 20060183328 - Electrolytic copper plating solutions The present invention provides inter alia copper electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention contain an increased brightener concentration that can provide effective copper plate on difficult-to-plate aperture walls, including high aspect ratio, small diameter microvias. ... 08/17/06 - 20060183327 - Nitrogen rich barrier layers and methods of fabrication thereof Methods of forming barrier layers and structures thereof are disclosed. A nitrogen rich region is formed at a top surface of a barrier layer by exposing the barrier layer to a nitridation treatment. The nitrogen rich region increases the oxidation resistance of the barrier layer. The barrier layers have improved ... 08/17/06 - 20060183326 - High pressure treatment for improved grain growth and void reduction A copper film is annealed at high pressure to enhance grain growth and remove voids. Other films, such as dielectrics, may also be suitable. High pressure can be used in conjunction with temperatures lower than room temperature for annealing or higher temperatures may be used to further enhance grain growth. ... 08/10/06 - 20060178008 - Post etch copper cleaning using dry plasma A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass of 15 or greater. ... 08/03/06 - 20060172536 - Apparatus for plasma-enhanced physical vapor deposition of copper with rf source power applied through the workpiece A method of performing physical vapor deposition of copper onto an integrated circuit in a vacuum chamber of a plasma reactor includes providing a copper target near a ceiling of the chamber, placing an integrated circuit wafer on a wafer support pedestal facing the target near a floor of the ... 07/13/06 - 20060154483 - Method of providing a structure using self-aligned features In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the ... 07/13/06 - 20060154482 - Semiconductor device An object of the invention is to make it possible to perform the embedding of a Cu diffusion preventing film and a Cu film to a fine pattern of a high aspect ratio by using a medium of a supercritical state in a manufacturing process of a semiconductor device. The ... 07/06/06 - 20060148255 - Method for cuo reduction by using two step nitrogen oxygen and reducing plasma treatment A method for cleaning a copper interconnect after a chemical-mechanical polishing that comprises: a) treating the surface of said copper interconnect with a nitrogen and oxygen containing treatment; and b) without breaking vacuum, treating the copper interconnect with a NH3 or H2 plasma treatment. Next a cap layer is formed ... 06/29/06 - 20060141785 - Inter-metal dielectric of semiconductor device and manufacturing method thereof An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer ... 06/29/06 - 20060141784 - Copper electrodeposition in microelectronics An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu ... 06/08/06 - 20060121734 - Semiconductor device A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving ... 05/18/06 - 20060105570 - Copper interconnect wiring and method of forming thereof Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use ... 03/02/06 - 20060046481 - Manufacturing methods and electroless plating apparatus for manufacturing wiring circuit boards A manufacturing method for wiring circuit boards enhances product yield and promotes uniform electrical characteristics among the products by reducing fluctuations in the thickness of the electroless Cu plating film. In a plating bath (53) containing an electroless Cu plating liquid (EPL), wiring circuit board workpieces (100) are held in ... 02/23/06 - 20060040498 - Method for manufacturing dual damascene structure with a trench formed first A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer ... 02/09/06 - 20060030151 - Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement An integrated sputtering method and reactor for copper or aluminum seed layers in which a plasma sputter reactor initially deposits a thin conformal layer onto a substrate including a high-aspect ratio hole subject to the formation of overhangs. After the seed deposition, the same sputter reactor is used to sputter ... 01/26/06 - 20060019496 - Method for fabricating copper-based interconnections for semiconductor device Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, and carrying out high temperature and ... 01/12/06 - 20060009037 - Method for fabricating metal line in a semiconductor A metal line is fabricated in a semiconductor device by a method including: forming an etch stop layer on a substrate; forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer including dual damascene patterns, each respectively having a trench and a via contact hole; forming ... 12/22/05 - 20050282385 - Conductive material patterning methods A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first ... 12/15/05 - 20050277298 - Adhesion of copper and etch stop layer for copper alloy A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual ... 12/15/05 - 20050277297 - Copper nanocrystals and methods of producing same The invention relates to methods of making monodisperse nanocrystals comprising the steps of reducing a copper salt with a reducing agent, providing a passivating agent comprising a nitrogen and/or an oxygen donating moitey and isolating the copper nanocrystals. Moreover, the invention relates to methods for making a copper film comprising ... 11/17/05 - 20050255700 - Controlled multi-step magnetron sputtering process A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault ... 11/10/05 - 20050250328 - Copper interconnection and the method for fabricating the same A copper interconnection where holes in the vicinity of an interface are reduced to lower contribution of interface diffusion to Cu the EM, increase a lifetime, and simultaneously increase adhesiveness and resistance to stress migration is constituted in a manner that impurities 15 form a solid solution in the vicinity ... 11/10/05 - 20050250327 - Copper plating of semiconductor devices using intermediate immersion step A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps ... 11/03/05 - 20050245084 - Filling high aspect ratio openings by enhanced electrochemical deposition (ecd) One embodiment of the invention is a method for void-free filling with a metal or an alloy inside narrow openings by electrochemical deposition (ECD), said method including steps of: (a) providing a substrate with electrically conductive surface, said conductive surface including at least one opening and a field surrounding the ... 11/03/05 - 20050245083 - Apparatus and method for electrochemically depositing metal on a semiconductor workpiece A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the ... 11/03/05 - 20050245082 - Process for removing organic materials during formation of a metal interconnect A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. ... 10/27/05 - 20050239288 - Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such ... 10/20/05 - 20050233586 - Method to reduce silanol and improve barrier properties in low k dielectric ic interconnects A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer ... 10/13/05 - 20050227488 - Capping of copper structures in hydrophobic ild using aqueous electro-less bath Capping of copper structures in hydrophobic interlayer dielectric layer, using aqueous electro-less bath is described herein. ... 09/01/05 - 20050191855 - Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower ... 08/25/05 - 20050186795 - Method of forming buried wiring in semiconductor device A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer ... 08/25/05 - 20050186794 - Method for fabricating semiconductor device In a method for fabricating a semiconductor device, interconnect grooves are formed in an insulating film on a substrate, and then a copper film is formed on the insulating film to fill the interconnect grooves. Subsequently, portions of the copper film existing outside the interconnect grooves are polished to form ... 08/25/05 - 20050186793 - Manufacturing method of semiconductor device There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, ... 08/04/05 - 20050170648 - Method to solve via poisoning for porous low-k dielectric A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer ... 07/21/05 - 20050158999 - Multi-step plasma treatment method to improve cu interconnect electrical performance A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process ... 07/14/05 - 20050153549 - Method of forming metal wiring for high voltage element Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form ... 07/14/05 - 20050153548 - Method for fabricating semiconductor device to minimize terminal effect in ecp process The method for fabricating a semiconductor device according to the present invention provides the improvement of uniformity by forming a seed layer with low-resistivity regardless of a thin thickness in order to avoid a terminal effect in an ECP process. ... 07/07/05 - 20050148176 - Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device, comprising the following processes of forming a structure in which a barrier metal containing at least of Ti and Ta and a copper wiring are exposed on its surface, or a structure in which at least one substance selected from the group consisting ... 06/30/05 - 20050142875 - Selective heating using flash anneal A copper film is treated by applying light at short wavelengths, e.g., at less than 0.6 μm, to heat the copper film and generate a large temperature gradient from the surface of the copper to the interface between the copper and underlying silicon. As a result, grain growth in the ... 06/30/05 - 20050142874 - Methods for fabricating a copper interconnect Methods for fabricating a copper interconnect are disclosed. A disclosed method comprises: employing a damascene process to form a first trench in a first insulating layer; depositing a first barrier layer and a first copper layer on the first insulating layer; forming a bottom copper interconnect by planarizing the first ... 06/23/05 - 20050136661 - Method for fabricating semiconductor device A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38; and concurrently injecting nitrogen gas and water to the surface of the interconnection ... 06/16/05 - 20050130419 - Method for reducing corrosion of metal surfaces during semiconductor processing A semiconductor process exposes metal in anticipation of an additional processing step that includes a deposition of a layer. Between the two processing steps, the exposed metal is exposed to ambient conditions that may include humidity. The effect of the humidity is potentially to cause corrosion of the exposed metal ... 06/02/05 - 20050118810 - Method of cleaning surface of semiconductor substrate, method of manufacturing thin film, method of manufacturing semiconductor device, and semiconductor device A technique that enables the formation of a low resistivity barrier film at low temperatures, and a technique that enables the removal of impurities (such as, oxides, fluorides, carbides, and nitrides) from the surfaces of semiconductor substrates and metal thin films at low temperatures. A catalyst is placed inside a ... 06/02/05 - 20050118809 - Manufacturing method of semiconductor device The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming ... 06/02/05 - 20050118808 - Method of reducing the pattern effect in the cmp process A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part ... ### FreshPatents.com Support |