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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Contacting Multiple Semiconductive Regions (i.e., Interconnects) > Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) > With Formation Of Opening (i.e., Viahole) In Insulative Layer > Having Viaholes Of Diverse Width Having Viaholes Of Diverse WidthHaving Viaholes Of Diverse Width patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087562 - Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the ... 03/15/07 - 20070059924 - Method of manufacturing semiconductor device According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming on a semiconductor substrate an insulating film having a recessed portion in a surface thereof, forming on the insulating film a first metal film so as to fill ... 03/01/07 - 20070049013 - Method and apparatus for manufacturing semiconductor device, control program and computer storage medium In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etching the insulating film through ... 03/01/07 - 20070049012 - Dual damascene structure and fabrication thereof A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal ... 02/22/07 - 20070042600 - Method for fabricating semiconductor device In a Cu interconnect process, an organic-based low-dielectric-constant interlayer film is formed, and then a protective film is deposited on the side and back surfaces of a wafer bevel and the back surface of a wafer edge. Thereafter, a lithography process and an etching process are carried out, a copper ... 02/22/07 - 20070042599 - Methods to facilitate etch uniformity and selectivity A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. ... 02/15/07 - 20070037385 - Metal interconnect structure and method A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive ... 02/08/07 - 20070032071 - Methods of forming cosi2, methods of forming field effect transistors, and methods of forming conductive contacts The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. ... 02/01/07 - 20070026670 - Method of reducing contamination by removing an interlayer dielectric from the substrate edge By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of ... 01/11/07 - 20070010092 - Method for eliminating bridging defect in via first dual damascene process A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two ... 12/28/06 - 20060292863 - Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered ... 11/23/06 - 20060264036 - Line level air gaps In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air ... 11/23/06 - 20060264035 - Crack stop trenches in multi-layered low-k semiconductor devices A method is provided for fabricating a semiconductor device. The method begins by forming on a substrate an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate. After forming the interconnect stack layer, a crack stop trench is formed in the interconnect stack layer. ... 11/16/06 - 20060258151 - Multi-layered copper line structure of semiconductor device and method for forming the same A multi-layered copper line structure of a semiconductor device with a lower copper line, an upper copper line, and a via contact, which electrically connects the lower copper line and the upper copper line, can incorporate one or more dummy via contacts to reduce the occurrence of voids in the ... 11/09/06 - 20060252258 - Low temperature method for minimizing copper hillock defects A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in ... 11/02/06 - 20060246718 - Technique for forming self-aligned vias in a metallization layer By designing trenches with portions of increased width, via structures formed after the trench etch process may be etched on the basis of sidewall spacers in the portions of increased widths, thereby rendering a further photolithography process for defining via openings obsolete. Consequently, high alignment precision with reduced process complexity ... 10/19/06 - 20060234498 - Method of performing a surface treatment respectively on the via and the trench in a dual damascene process The present invention provides a method of performing a surface treatment respectively on the via and the trench in a dual damascene process by the plasma having the inclined angle. The residual and/or the metal surface oxide on the bottom of the via are removed in the via and the ... 10/19/06 - 20060234497 - Interconnect structure and method of fabrication of same A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing ... 10/12/06 - 20060228884 - Unidirectionally conductive materials for interconnection A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may ... 09/14/06 - 20060205207 - Method for forming dual damascene with improved etch profiles A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the hardmask layer; forming a trench line opening through at least the thickness of ... 09/07/06 - 20060199380 - Imprinting-damascene process for metal interconnection The present invention first obtains a nano-metal line by an e-beam lithography and an electroless plating, and imprints the line into a material with low-K to obtain a damascene metal line with low cost and high throughput, as a future solution for a metallization process for a general low-K metal ... 09/07/06 - 20060199379 - Method for forming dual damascene structures with tapered via portions and improved performance The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is ... 08/24/06 - 20060189127 - Method to improve palanarity of electroplated copper Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling ... 07/06/06 - 20060148243 - Method for fabricating a dual damascene and polymer removal A method for fabricating a dual damascene includes a partial etching process, a photoresist layer stripping process, and a blanket etching process. After the blanket etching process, an in-situ dry cleaning process is performed to remove residual polymers resulting from the etching processes. ... 06/29/06 - 20060141778 - Manufacturing method of semiconductor device A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a ... 06/29/06 - 20060141777 - Methods for patterning a layer of a semiconductor device A patterning layer of a single or multiple layer structure formed on a lower layer may be etched to form one or more steps therein, when the patterning layer is first dry etched to a partial depth thereof using a first resist pattern and then the patterning layer is etched ... 06/29/06 - 20060141776 - Method of manufacturing a semiconductor device Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist ... 06/29/06 - 20060141775 - Method of forming electrical connections in a semiconductor structure A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a material formed on a first surface of the substrate. At least one recess is formed in the layer of material. The formation of the at least one recess comprises performing a dry etching process. ... 06/15/06 - 20060128142 - Method for selective deposition of a thin self-assembled monolayer A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface ... 06/08/06 - 20060121730 - Method of forming damascene structures A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. A gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photoresist pattern for ... 06/08/06 - 20060121729 - Methods for the optimization of ion energy control in a plasma processing system A method in a plasma processing system for etching a feature through a dielectric layer of a dual damascene stack on a semiconductor substrate is disclosed. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method further includes flowing an etchant gas ... 06/01/06 - 20060115982 - Method for manufacturing semiconductor device It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a contact hole with an opening having a high aspect ratio can be favorably filled without using a conventional CMP process. It is another object of the present invention to provide ... 06/01/06 - 20060115981 - Forming a dual damascene structure without ashing-damaged ultra-low-k intermetal dielectric A new method for forming a single or a double damascene interconnect structure is provided in which after the damascene interconnect structure is formed, in which a plasma ashing process is used to remove the photoresist mask used during the photolithography process, the trench-level intermetal dielectric layer is removed leaving ... 05/04/06 - 20060094234 - Method for manufacturing electonic device A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The ... 03/23/06 - 20060063376 - Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical ... 03/09/06 - 20060051958 - Dual damascene process with dummy features A method for creating a hole in a semiconductor wafer includes forming a hard mask over a dielectric layer, the hard mask including a solid portion and a first opening. A patterning layer is provided over the hard mask, the patterning layer including second and third openings. The second opening ... 03/02/06 - 20060046471 - Methods for forming vias of varying lateral dimensions and semiconductor components and assemblies including same Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening and a second opening are formed in a substrate such that the first opening and the second opening are in communication with each other. A portion ... 02/23/06 - 20060040492 - Formation of air gaps in an interconnect structure using a thin permeable hard mask and resulting structures A method of forming air gaps in the interconnect structure of an integrated circuit device. The air gaps may be formed by depositing sacrificial layer over a dielectric layer and then depositing a permeable hard mask over the sacrificial layer. The sacrificial layer is subsequently removed to form air gaps. ... 02/02/06 - 20060024958 - Hsq/sog dry strip process A spin-on dielectric (120) strip process. Instead of a wet strip, a dry strip process is used to remove the spin-on dielectric (120). In a via-first dual damascene method, a via (116) may be patterned and etched and the via (116) is filled with the spin-on dielectric (120). Then, the ... 01/26/06 - 20060019491 - Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second ... 01/19/06 - 20060014382 - Method for forming an interconnection line in a semiconductor device The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist ... 01/19/06 - 20060014381 - Method for forming interconnection line in semiconductor device using a phase-shift photo mask A method for forming a dual damascene structure. The method includes depositing an interlayer dielectric on an underlying layer, depositing a photoresist on the interlayer dielectric, and exposing and developing the photoresist by using a phase-shift photo mask to form a photoresist pattern having trench patterns and hole patterns. The ... 01/05/06 - 20060003578 - Method of manufacturing a semiconductor device The present invention relates to a method of manufacturing a semiconductor device which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. According to the present invention, even though a contact or via is electrically shorted, it is ... 01/05/06 - 20060003577 - Method of manufacturing a semiconductor device To effectively reduce the dielectric constant of an interlayer insulation film including a low dielectric constant film of a porous structure, and easily realize a practical application of a semiconductor device having an ultrafine and highly reliable Damascene wiring structure. A first interlayer insulation film including a porous first low ... 01/05/06 - 20060003576 - Dual damascene trench formation to avoid low-k dielectric damage A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask ... 12/29/05 - 20050287797 - Method of making a semiconductor device manufacturing mask substrate A method of making a semiconductor device manufacturing mask, which makes it possible to suppress a semiconductor-device global step and simply manufacture a highly reliable semiconductor device. Square dummy patterns each having one side of, for example, 0.25 μm or less are inserted into an area other than an actual ... 12/29/05 - 20050287796 - Methods of fabricating metal lines in semiconductor devices Methods to form metal lines in semiconductor devices are disclosed. An illustrated method comprises: depositing first and second interlayer dielectric layers on a semiconductor substrate; forming a via hole in the second interlayer dielectric; forming a photoresist pattern, forming a trench, using the photoresist pattern as a mask; removing an ... 12/01/05 - 20050266683 - Remover compositions for dual damascene system A new remover chemistry based on a choline compound, such as choline hydroxide, is provided in order to address problems related to removal of residues, modified photoresists, photoresists, and polymers such as organic anti-reflective coatings and gap-fill and sacrificial polymers from surfaces involved in dual damascene structures without damaging the ... 11/24/05 - 20050260850 - Low-carbon-doped silicon oxide film and damascene structure using same A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming a dielectric layer on the second hard ... 11/17/05 - 20050255697 - Selective etching of organosilicate films over silicon oxide stop etch layers A method of selectively etching organosilicate layers in integrated circuit fabrication processes is disclosed. The organosilicate layers are selectively etched using a hydrogen-containing fluorocarbon gas. The hydrogen-containing fluorocarbon gas may be used to selectively etch an organosilicate layer formed on a silicon oxide stop etch layer when fabricating a damascene ... 11/03/05 - 20050245075 - Semiconductor device and method of manufacturing same Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second ... 08/25/05 - 20050186782 - Dual damascene interconnect structure with improved electro migration lifetimes A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity ... 07/28/05 - 20050164495 - Method to improve planarity of electroplated copper Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling ... 07/14/05 - 20050153542 - Method for forming dual damascene pattern Disclosed is a method for forming a dual damascene pattern. The method comprises the steps of forming a lower conductive structure on a lower insulating layer, forming a first protective film, a first insulating film, a second insulating film, a third insulating film, and a second protective film, sequentially, on ... 07/14/05 - 20050153541 - Method of forming metal wiring in a semiconductor device A method of forming metal wiring in a semiconductor device is disclosed. The method uses a dual damascene process in which a trench is formed prior to a via-hole. ... 06/30/05 - 20050142860 - Method for fabricating metal wirings of semiconductor device A method for fabricating metal wirings of a semiconductor including forming an etch stop layer on a semiconductor substrate, and forming an inter metal dielectric on the etch stop layer. The method also includes forming a via hole in the inter metal dielectric so as to expose the etch stop ... 06/30/05 - 20050142859 - Method for forming contact hole for dual damascene interconnection in semiconductor device A method for forming a contact hole for a dual damascene interconnection in a semiconductor device. A via hole is formed to expose an etch stop film on a lower metal film through an intermetal insulating film. The via hole is filled with a sacrificial film. A bottom antireflective coating ... 06/30/05 - 20050142858 - Method of forming barrier metal in semiconductor device A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall ... 06/30/05 - 20050142857 - Method for forming metal line in semiconductor device The present invention discloses a method for forming a metal line in a semiconductor device which can prevent metal plating from being protruded from a specific portion, prevent bridges from being generated between metal lines by a uniform thickness, and improve reliability of the process, by forming a dual damascene ... 06/23/05 - 20050136651 - Metal interconnection structure of semiconductor device and method of forming the same Provided is a metal interconnection structure of a semiconductor device, having: a lower metal layer disposed on an insulating layer formed on a semiconductor device; a contact plug disposed on the lower metal layer; a supporting layer disposed to surround the contact plug; an upper metal layer disposed on the ... ### FreshPatents.com Support |