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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Contacting Multiple Semiconductive Regions (i.e., Interconnects) > Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) > With Formation Of Opening (i.e., Viahole) In Insulative Layer With Formation Of Opening (i.e., Viahole) In Insulative LayerWith Formation Of Opening (i.e., Viahole) In Insulative Layer patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087561 - Method for making an opening for electrical contact by etch back profile control A method and apparatus for etchback profile control. The method includes performing a first etch through a first dielectric layer to form a first via and a second dielectric layer, filling the first via with a BARC material to form a first BARC layer, and performing a second etch on ... 04/19/07 - 20070087560 - Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a ... 04/12/07 - 20070082484 - Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step ... 04/12/07 - 20070082483 - Method of etching carbon-containing layer and method of fabricating semiconductor device A method of etching a carbon-containing layer on a semiconductor substrate using a Si-containing gas and a related method of fabricating a semiconductor device in which a plurality of contact holes having excellent sidewall profiles are formed by etching an interlayer insulating layer using a carbon-containing layer pattern formed in ... 04/12/07 - 20070082482 - Method for forming contact hole of semiconductor device A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive patterns. A hard mask including an amorphous carbon layer and an oxide based layer are formed in sequential order ... 03/29/07 - 20070072411 - Method for forming metal line in semiconductor device A method for forming a metal line in a semiconductor device includes forming a plug buried in an inter-layer insulation layer formed over a substrate, forming a metal line layer over the plug and the substrate, forming a contact mask over the metal line layer, etching first portions of the ... 03/15/07 - 20070059923 - Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening ... 03/15/07 - 20070059922 - Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structure The present invention relates to methods for post-etch, particularly post-RIE, removal of fluorocarbon-based residues from a hybrid dielectric structure. The hybrid dielectric structure contains a first dielectric material, and a line-level dielectric layer containing a second, different dielectric material, and wherein said second, different dielectric material comprises a polymeric thermoset ... 03/08/07 - 20070054486 - Method for forming opening A method for forming an opening. The method comprises steps of providing a substrate having at least one element structure formed thereon and then forming a dielectric layer over the substrate to cover the element structure. A patterned metal silicide layer is formed on the dielectric layer and then the ... 03/01/07 - 20070049011 - Method of forming isolated features using pitch multiplication Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed ... 02/15/07 - 20070037384 - A method for processing ic designs for different metal beol processes A method for processing IC designs for different metal BEOL processes is provided for enabling fabricating using a metal fabrication process an IC originally having a backend design for a different metal fabrication process. The method first determines layer constructions of an original design of an IC for a first ... 02/01/07 - 20070026669 - Semiconductor device and method of fabricating the same A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under ... 02/01/07 - 20070026668 - Low k dielectric surface damage control A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying ... 02/01/07 - 20070026667 - Composition for forming etching stopper layer An object of the present invention is to provide a composition for formation of etching stopper layer, which can simultaneously realize dry etching selectivity and low permittivity, and a production process of a semiconductor device using the same. This object can be attained by a composition for formation of etching ... 01/25/07 - 20070020922 - Method of depositing a metal seed layer on semiconductor substrates We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material ... 01/25/07 - 20070020921 - Prevention of trench photoresist scum Methods of preventing photoresist scum formation for etch processes for patterning material layers of semiconductor device material layers are disclosed. A treatment of N2 and O2 is used to prevent the formation of photoresist scum. The treatment may be performed in-situ, and may be performed during the etch process, after ... 01/18/07 - 20070015356 - Method for forming contact hole in semiconductor device A method for forming a contact hole in a semiconductor device is provided. A method for forming a contact hole in a semiconductor device includes: forming an insulation layer over a bottom structure; forming a hard mask pattern over the insulation layer; etching a portion of the insulation layer using ... 01/11/07 - 20070010091 - Method for performing chemical shrink process over barc (bottom anti-reflective coating) A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist ... 12/28/06 - 20060292862 - Method for forming barrier metal of semiconductor device A method for forming a barrier metal of a semiconductor device includes forming an insulating layer on a semiconductor substrate and forming an opening in the insulating layer and forming a TiSiN layer having a desired thickness by repeatedly performing a process of forming a TiSiN layer having an atomic ... 12/21/06 - 20060286795 - Method of manufacturing semiconductor device A method for manufacturing a semiconductor device is provided, which comprises forming a first metal wiring layer above a semiconductor substrate, forming an inorganic insulating film above the first metal wiring layer, forming an organic insulating film on the inorganic insulating film, forming a recess in the organic insulating film, ... 12/21/06 - 20060286794 - Stacked structure for forming damascene structure, method of fabricating the stacked structure, and damascene process A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in ... 12/21/06 - 20060286793 - Stacked structure for forming damascene structure, method of fabricating the stacked structure, and damascene process A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in ... 12/07/06 - 20060276032 - Fabrication method for a semiconductor device There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask ... 11/30/06 - 20060270216 - Phase change memory cell defined by a pattern shrink material process One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second electrode adjacent the phase-change material. The phase-change material has a sublithographic width defined by a pattern shrink material process. ... 11/30/06 - 20060270215 - Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the semiconductor device may include a layered structure and a plug. The layered structure may have a lower insulation layer pattern, a single crystalline silicon pattern, and an upper insulation layer pattern provided on a substrate. A contact hole may be provided ... 11/30/06 - 20060270214 - Semiconductor device and method for fabricating the same When a via-hole 26 and an interconnection trench 32 are formed in an interconnection films 16, 18 by using as a mask a hard mask 20 covering the region except via-hole forming region, and a hard mask 22 covering the region except an interconnection trench forming region, the hard mask ... 11/23/06 - 20060264034 - Semiconductor device A semiconductor device comprises a plurality of semiconductor elements; and a first wire and a second wire provided to connect the semiconductor elements in parallel. The first wire and the second wire include respective wires formed in multiple wiring layers. Each wiring layer includes the first wire and the second ... 11/23/06 - 20060264033 - Dual damascene patterning method A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning ... 11/09/06 - 20060252257 - Method of forming isolation structure of semiconductor device A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the ... 11/09/06 - 20060252256 - Method for removing post-etch residue from wafer surface A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped ... 11/09/06 - 20060252255 - Focused ion beam deposition Introducing at least one metal such as cobalt, molybdenum, metal carbonyl, tungsten, platinum, or other suitable metal to a focused ion beam. Introducing the focused ion beam to a substrate within a processing chamber. Forming at least one layer over a substrate. Applying heat to the layer by, for example, ... 11/02/06 - 20060246717 - Method for fabricating a dual damascene and polymer removal A method for fabricating a dual damascene includes a partial etching process, a photoresist layer stripping process, and a blanket etching process. After the blanket etching process, an in-situ dry cleaning process is performed to remove residual polymers resulting from the etching processes. ... 11/02/06 - 20060246716 - Semiconductor cmos devices and methods with nmos high-k dielectric formed prior to core pmos dielectric formation The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. ... 10/26/06 - 20060240663 - Methods of forming a resistance variable element The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The ... 10/19/06 - 20060234496 - Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in ... 10/19/06 - 20060234495 - Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity Numerous embodiments of a method to assay sacrificial material are disclosed. In one embodiment, a sacrificial material may be analyzed by high performance liquid chromatography. Chemical markers that correlate with material contaminants in the sacrificial material may be identified. ... 10/12/06 - 20060228883 - Phase change memory cell defined by a pattern shrink material process One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second electrode adjacent the phase-change material. The phase-change material has a sublithographic width defined by a pattern shrink material process. ... 10/05/06 - 20060223306 - Method for forming film, method for manufacturing semiconductor device, semiconductor device and substrate treatment system A film forming method comprise the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio, defined as a ratio of a number of F atoms to a number ... 09/28/06 - 20060216930 - Post ecp multi-step anneal/h2 treatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process ... 09/28/06 - 20060216929 - Etch stopless dual damascene structure and method of fabrication An etch stopless interconnect structure. According to embodiments of the present invention, a via opening is formed in an interlayer dielectric over a metal layer to expose a portion of the metal layer. The opening is then partially filled with a gap fill material. The opening is then filled with ... 09/21/06 - 20060211238 - Manufacture of semiconductor device with good contact holes A wiring layer having an antireflection film of TiN or the like is formed on an insulating film covering a principal surface of a semiconductor substrate, and thereafter an interlayer insulating film including first to third insulating films is formed covering the wiring layer. The first and third insulating films ... 09/14/06 - 20060205206 - Method of eliminating photoresist poisoning in damascene applications A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a plasma of an inert gas, and depositing a photoresist on the dielectric layer comprising silicon and carbon. The dielectric ... 09/07/06 - 20060199378 - Method of manufacturing semiconductor device In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched ... 09/07/06 - 20060199377 - Method for fabricating a resistively switching nonvolatile memory cell A method for fabricating a resistively switching memory cell is provided. The method includes the following steps: depositing a first electrode, applying a layer of a chalcogenide compound to the first electrode, applying a layer of silver or copper, and operating a noble gas plasma in a back-sputtering mode in ... 09/07/06 - 20060199376 - Manufacturing method for semiconductor device A semiconductor device manufacturing method for suppressing surface roughness of a Low-k insulating film during etching. In a laminated structure comprising a layer having formed thereon a lower copper wiring, a SiC film and a SiOC film, a via and an upper copper wiring are formed as follows. The SiOC ... 08/17/06 - 20060183320 - Methods of filling trenches using high-density plasma deposition (hdp) Methods of filling trenches/gaps defined by circuit elements on an integrated circuit substrate are provided. The methods include forming a first high-density plasma layer on an integrated circuit substrate including at least one trench thereon using a first reaction gas. The first high-density plasma layer is etched using an etch ... 08/17/06 - 20060183319 - Method for manufacturing a semiconductor device In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having ... 08/10/06 - 20060178005 - Pattern formation method A resist film is first formed on a substrate. Subsequently, a first barrier film including a water-soluble solvent is formed on the resist film, and a second barrier film including an alcoholic solvent is formed on the first barrier film. Thereafter, with a liquid provided on the second barrier film, ... 08/10/06 - 20060178004 - Method of obtaining release-standing micro structures and devices by selective etch removal of protective and sacrificial layer using the same A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film ... 08/03/06 - 20060172531 - Sealing pores of low-k dielectrics using cxhy A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this ... 08/03/06 - 20060172530 - Cxhy sacrificial layer for cu/low-k interconnects A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments ... 08/03/06 - 20060172529 - Uniform passivation method for conductive features The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the ... 07/27/06 - 20060166493 - Semiconductor device having nitridated oxide layer and method therefor A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to ... 07/27/06 - 20060166492 - Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably ... 07/27/06 - 20060166491 - Dual damascene interconnection having low k layer and cap layer formed in a common pecvd process A method of fabricating dual damascene interconnections begins by forming on a substrate a dielectric layer by a PECVD process that employs a first precursor gas. A capping layer is formed on the dielectric layer by a PECVD process that also employs the first precursor gas such that deposition of ... 07/20/06 - 20060160356 - Method for fabricating self-aligned contact hole Disclosed are: (i) a method for fabricating self-aligned contact hole in a semiconductor device, and (ii) a semiconductor device having a self-aligned contact. The method comprises the steps of: (a) forming an oxide layer covering a gate structure on a semiconductor substrate, the gate structure including a gate oxide pattern, ... 07/20/06 - 20060160355 - Semiconductor device with a metal line and method of forming the same A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an FSG (Fluorine-doped Silicate Glass) layer, and ... 07/13/06 - 20060154478 - Contact hole structures and contact structures and fabrication methods thereof Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without ... 07/13/06 - 20060154477 - Polymer spacer formation A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall ... 07/13/06 - 20060154476 - Bipolar transistor with collector having an epitaxial si:c region A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region ... 07/06/06 - 20060148242 - Metallization method of semiconductor device A method for forming a metallization contact in a semiconductor device includes the steps of: (a) forming an insulating layer on a semiconductor substrate including an active device region; (b) forming a contact hole to expose a portion of the active device region by etching a portion of the insulating ... 07/06/06 - 20060148241 - System for and method of forming via holes by use of selective plasma etching in a continuous inline shadow mask deposition process In a shadow mask vapor deposition system, a first conductor is vapor deposited on a substrate and an insulator is vapor deposited on the first conductor. A second conductor is then vapor deposited on at least the insulator. The insulator layer is plasma etched either before or after the vapor ... 06/29/06 - 20060141774 - Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure A mask pattern (110) of a pattern transfer mask (101) includes a light shielding pattern (111) and a light transmitting pattern (112). The light shielding pattern (111) has a shape (pattern) subjected to undersizing near portions corresponding to via holes (51H). It is desirable to make undersizing to a greater ... 06/29/06 - 20060141773 - Method of forming metal line in semiconductor device A method of forming a metal line in a semiconductor device reduces production costs through a simplified fabricating process. The method includes steps of forming a first metal line on a semiconductor substrate; forming an insulating layer over the semiconductor substrate including the first metal line; coating a photoresist on ... 06/29/06 - 20060141772 - Methods of forming interconnection lines in semiconductor devices The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first ... 06/22/06 - 20060134910 - Method of forming contact hole and method of fabricating semiconductor device A method of forming contact holes is provided. A substrate having a plurality of device structures is provided. A first dielectric layer and a conductive layer sequentially cover the device structures and the surface of the substrate. A recess is formed in the conductive layer between every two neighboring device ... 06/22/06 - 20060134909 - Method for fabricating semiconductor device The method for fabricating the semiconductor device comprises the step of forming an insulating film 14 having an opening 18; the step of forming an organic resist film 20a; the step of forming over the organic resist film 20a a mask film 20b having etching characteristics different from those of ... 06/15/06 - 20060128141 - Semiconductor device and method for fabricating the same An insulating film is formed of a carbon-containing silicon dioxide film on a semiconductor substrate. In the insulating film, an interconnect groove is formed. A silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of ... 06/15/06 - 20060128140 - Method of forming a contact hole in a semiconductor device An exemplary method of forming a contact hole in a semiconductor device includes: forming a first insulation layer on a lower substrate; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first insulation layer and the first conductive layer; forming a second ... 06/15/06 - 20060128139 - Process sequence for doped silicon fill of deep trenches A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way ... 06/08/06 - 20060121728 - Method for fast filling of templates for imprint lithography using on template dispense A method of depositing material upon a substrate features filling recesses of a substrate with liquid and removing material present on the substrate, outside of the recesses using fluid, i.e., apply a vacuum of a jet of fluid. To that end, one method of the present invention includes depositing a ... 06/08/06 - 20060121727 - Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode A method for making a titanium carbide layer is described. That method comprises alternately introducing a carbon containing precursor and a titanium containing precursor into a chemical vapor deposition reactor, while a substrate is maintained at a selected temperature. The reactor is operated for a sufficient time, and pulse times ... 06/08/06 - 20060121726 - Methods of depositing silver onto a metal selenide-comprising surface, methods of depositing silver onto a selenium-comprising surface, and methods of forming a resistance variable device The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The ... 06/01/06 - 20060115980 - Method for decreasing a dielectric constant of a low-k film A method of forming a low dielectric constant film that can be used in a damascene process is disclosed. An organosilicon precursor such as octamethylcyclotrisiloxane (OMCTS) or any other compound that contains Si, C, and H and optionally O is transported into a PECVD chamber with a carrier gas such ... 06/01/06 - 20060115979 - Plasma etch process for multilayer vias having an organic layer with vertical sidewalls A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer ... 06/01/06 - 20060115978 - Charge-trapping memory cell and method for production The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer ... 05/18/06 - 20060105567 - Method for forming a dual-damascene structure A dual-damascene structure is formed in a porous dielectric material using an anti-reflective coating. In accordance with one embodiment, during patterning and etching if the trench portions of the dual-damascene structure, the anti-reflective coating has a first density. After patterning and etching, the anti-reflective coating density is reduced. The reduction ... 05/18/06 - 20060105566 - Ultraviolet assisted pore sealing of porous low k dielectric films Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface ... 05/11/06 - 20060099802 - Diffusion barrier for damascene structures A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material. ... 05/11/06 - 20060099801 - Method and structure to wire electronic devices An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size ... 05/04/06 - 20060094233 - Device and method for determining an edge coverage during coating processes In a method for determining an edge coverage during coating processes a substrate is provided, a mask layer is deposited on the substrate, at least one through hole is formed in the mask layer and at least one first trench-type depression is formed in the substrate by patterning the substrate ... 05/04/06 - 20060094232 - Methods of forming planarized multilevel metallization in an integrated circuit A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium ... 05/04/06 - 20060094231 - Method of creating a tapered via using a receding mask and resulting structure Embodiments of a method of forming a tapered via using a receding mask are disclosed. In one embodiment, an etch mask formed on a substrate includes a first aperture in a first photoresist layer and a second, larger aperture in an overlying second photoresist layer. Peripheries of the first and ... 05/04/06 - 20060094230 - Multiple layer resist scheme implementing etch recipe particular to each layer Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the ... 04/27/06 - 20060088996 - Buffer zone for the prevention of metal migration Particle migration, such as silver electro-migration, on a flat ceramic surface is effectively eliminated by an upward vertical barrier formed on the surface or a groove formed in the surface between two silver conductors. ... 04/13/06 - 20060079082 - Trench cut light emitting diodes and methods of fabricating same A method is provided for forming semiconductor devices using a semiconductor substrate having first and second opposed sides, and at least one device layer on the second side of the substrate, the at least one device layer including first and second device portions. A first trench is formed in the ... 04/06/06 - 20060073698 - Plasma enhanced nitride layer An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer ... 03/16/06 - 20060057843 - Methods and apparatus for forming barrier layers in high aspect ratio vias In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of ... 03/16/06 - 20060057842 - Ultra-thick metal-copper dual damascene process Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; ... 03/09/06 - 20060051957 - Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. ... 03/02/06 - 20060046470 - Apparatus and plasma ashing process for increasing photoresist removal rate A plasma ashing process for removing photoresist material and post etch residues from a substrate comprising carbon, hydrogen, or a combination of carbon and hydrogen, wherein the substrate comprises a low k dielectric layer, the process comprising forming a plasma from an essentially oxygen free and nitrogen free gas mixture; ... 03/02/06 - 20060046469 - Method for manufacturing a semiconductor device A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diffusion barrier on the etch stop layer, forming a via hole ... 03/02/06 - 20060046468 - Through-substrate interconnect fabrication methods and resulting structures and assemblies A method for forming a conductive via or through-wafer interconnect (TWI) in a semiconductive substrate for use as a contact card, test connector, semiconductor package interposer, or die interconnect includes the acts of (a) forming an oxide or nitride layer on both sides of the substrate, (b) forming a precursor ... 03/02/06 - 20060046467 - Organic solvents having ozone dissolved therein for semiconductor processing utilizing sacrificial materials A method of fabricating a semiconductor device. The method comprises creating a via in a dielectric layer that is formed on a substrate, filling the via, and optionally, the surface of the dielectric layer with a sacrificial material, patterning a first photoresist layer on the sacrificial material to define a ... 02/23/06 - 20060040491 - Slot designs in wide metal lines A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that ... 02/16/06 - 20060035459 - Method of forming narrowly spaced flash memory contact openings and lithography masks A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the ... 02/02/06 - 20060024957 - Methods for forming contact hole, for manufacturing circuit board and for manufacturing electro-optical device A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using ... 02/02/06 - 20060024956 - Method of eliminating etch ridges in a dual damascene process A dual damascene process employs a via fill material (38) with an etch rate that is within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which a trench (48) and via (50) are being formed. In one embodiment, an ... 01/26/06 - 20060019490 - Structure of gold bumps and gold conductors on one ic die and methods of manufacturing the structures A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first ... 01/26/06 - 20060019489 - Method for forming storage node contact of semiconductor device Disclosed is a method for forming a storage node contact of a semiconductor device. In such a method, there is provided a substrate formed with gates and source/drain regions. A landing plug poly is formed between the gates, and an insulating interlayer is formed over the entire surface of the ... 01/26/06 - 20060019488 - Method of forming a static random access memory with a buried local interconnect An SRAM cell includes six transistors. The storage nodes are implemented using local interconnects. A first level of metal overlies the interconnects but is electrically isolated therefrom. Contact plugs are formed to couple the cell to the first level of metal. The contact plugs are preferably formed in a different ... 01/26/06 - 20060019487 - Ferromagnetic liner for conductive lines of magnetic memory cells and methods of manufacturing thereof Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole ... 01/12/06 - 20060009031 - Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate - therein The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; forming an opening in the dielectric; and forming a ... 01/12/06 - 20060009030 - Novel barrier integration scheme for high-reliability vias Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a ... 01/12/06 - 20060009029 - Wafer level through-hole plugging using mechanical forming technique A wafer is provided having at least one through-hole therein. The at least one through-hole is filled with one or more conductive balls. Thereafter, the wafer is compressed wherein the one or more conductive balls form a conductive plug in the at least one through-hole. After forming the conductive plug ... 12/29/05 - 20050287795 - Method of forming high aspect ratio structures An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external ... 12/29/05 - 20050287794 - Contact structure This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more ... 12/22/05 - 20050282383 - Systems for forming insulative coatings for via holes in semiconductor devices An insulative coating for an aperture of a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually adhered regions may be formed by programmed material consolidation processes, such as stereolithography. Such an insulative coating may electrically isolate conductive features, such as conductive vias, from the ... 12/22/05 - 20050282382 - Method of preventing photoresist poisoning of a low-dielectric-constant insulator A method comprises forming a low-dielectric constant (low-k) layer over a semiconductor substrate, forming an anti-reflective layer over the low-k layer, forming at least one opening in the anti-reflective layer and in the low-k layer, forming a nitrogen-free liner in the at least one opening, and forming at least one ... 12/22/05 - 20050282381 - Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the ... 12/15/05 - 20050277289 - Line edge roughness reduction for trench etch A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is ... 12/15/05 - 20050277288 - Stackable semiconductor chip layer comprising prefabricated trench interconnect vias A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations ... 12/15/05 - 20050277287 - Contact etching utilizing multi-layer hard mask A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard ... 12/15/05 - 20050277286 - Metallic glass microtool Embodiments of the invention provide microtool made at least partially from a metallic glass material. The metallic glass material may allow formation of smaller features than achieved with other materials. The microtool may be used in some embodiments to form a package substrate with small feature sizes. ... 12/08/05 - 20050272256 - Semiconductor device and fabricating method thereof A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of ... 12/01/05 - 20050266682 - Methods and apparatus for forming barrier layers in high aspect ratio vias In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of ... 12/01/05 - 20050266681 - Formation of low resistance via contacts in interconnect structures A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) forming single or dual damascene etched ... 12/01/05 - 20050266680 - Methods of fabricating complex blade geometries from silicon wafers and strengthening blade geometries Ophthalmic surgical blades are manufactured from either a single crystal or poly-crystalline material, preferably in the form of a wafer. The method comprises preparing the single crystal or poly-crystalline wafers by mounting them and etching trenches into the wafers using one of several processes. Methods for machining the trenches, which ... 12/01/05 - 20050266679 - Barrier structure for semiconductor devices A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another ... 12/01/05 - 20050266678 - Source lines for nand memory devices Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected ... 11/24/05 - 20050260849 - Top layers of metal for high performance ic's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within ... 11/24/05 - 20050260848 - Method of forming a recessed structure employing a reverse tone process The present invention provides a method of forming recesses on a substrate, the method including forming on the substrate a patterning layer having first features; trim etching the first features to define trimmed features having a shape; and transferring an inverse of the shape into the substrate. ... 11/24/05 - 20050260847 - Method for forming contact window A method for forming a contact window is provided. First, a substrate is provided. On the substrate a dielectric layer is formed. Then, the dielectric layer is etched to form an opening, which defines a sidewall. Afterwards, on the sidewalls a low leakage dielectric isolation layer is formed. Finally, a ... 11/17/05 - 20050255696 - Method of processing resist, semiconductor device, and method of producing the same A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of ... 11/17/05 - 20050255695 - Decreasing the residue of a silicon dioxide layer after trench etching A semiconductor device is formed using a BARC (bottom antireflective coating) that minimizes the formation of fences around the via holes. The BARC is formed from an organic antireflective layer over an inorganic antireflective layer. The organic antireflective layer also covers the internal surface of the via hole. Subsequent treatment ... 11/10/05 - 20050250316 - Methods for fabricating memory devices using sacrifical layers and memory devices fabricated by same Methods are provided for fabricating contacts in integrated circuit devices, such as phase-change memories. A protection layer and a sacrificial layer are sequentially formed on a semiconductor substrate. A contact hole is formed through the sacrificial layer and the protection layer. A conductive layer is formed on the sacrificial layer ... 11/10/05 - 20050250315 - Methods of forming electrical connections for semiconductor constructions The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has ... 11/03/05 - 20050245074 - In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures One or more aspects of the subject disclosure pertain to forming single or dual damascene interconnect structures in the fabrication of semiconductor devices. The interconnect structures are formed in manners that mitigate one or more adverse effects associated with conventional techniques. One or more aspects of the invention may be ... 10/27/05 - 20050239286 - Two-step stripping method for removing via photoresist during the fabrication of partial-via dual damascene features A two-step stripping method for removing via photoresist during the fabrication of trench-first partial-via dual damascene features is disclosed. In the first cleaning step, inert gas (He, Ar, N2)/fluorocarbon plasma is used to contact the remaining “Via Photo” for a short time period not exceeding 20 seconds. Thereafter, in the ... 10/27/05 - 20050239285 - Damascene process capable of avoiding via resist poisoning A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k≦2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused ... 10/27/05 - 20050239284 - Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The ... 10/20/05 - 20050233580 - Alignment pattern for a semiconductor device manufacturing process An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over the surface of the substrate and a flat surface of a metal plug, and the flat ... 10/20/05 - 20050233579 - Method for forming metal wires in semiconductor device The present invention provides a method that can prevent an anti-diffusion film from being formed defectively on a porous dielectric film due to pores in method for forming metal wires in a semiconductor device in which the porous dielectric film is used as an insulating film between metal wires. The ... 10/13/05 - 20050227481 - Solid-state circuit assembly The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to ... 10/13/05 - 20050227480 - Low dielectric semiconductor device and process for fabricating the same A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning ... 10/13/05 - 20050227479 - Post ecp multi-step anneal/h2 treatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process ... 10/06/05 - 20050221610 - Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar ... 10/06/05 - 20050221609 - Mask, method for manufacturing a mask, method for manufacturing an electro-optical device, and electronic equipment A mask includes a silicon member, and a portion defining an opening penetrating the silicon member; and the corner of the opening is rounded. ... 09/15/05 - 20050202671 - Interconnect structure and method for fabricating the same A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric ... 09/08/05 - 20050196958 - Liquid discharge head and manufacturing method thereof The liquid discharge head comprises: a three-dimensional structure which defines a space including a pressure chamber filled with liquid and a flow channel for supplying the liquid to the pressure chamber, the three-dimensional structure being formed by depositing a composition material on a substrate according to a deposition method; and ... 09/08/05 - 20050196957 - Semiconductor device manufacturing method thereof This invention provides an etching method for preventing deformation of an opening without extremely lowering productivity. This invention has a process for bonding a supporting board on a front surface of a semiconductor substrate to cover a pad electrode formed on the semiconductor substrate with a silicon oxide film interposed ... 09/01/05 - 20050191852 - Method for manufacturing semiconductor device After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride film (6), an oxide layer (7) is formed on the surface of ... 08/25/05 - 20050186781 - Method for fabricating semiconductor device by forming damascene interconnections A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, ... 08/11/05 - 20050176242 - Patterning method A substrate is patterned by forming an indent region 8 in the surface 10 of a substrate 4 and depositing a liquid material onto the surface 10 at selected locations adjacent to the indent region 8. The liquid material spreads over the surface to an edge of the indent region, ... 08/04/05 - 20050170643 - Forming method of contact hole, and manufacturing method of semiconductor device, liquid crystal display device and el display device When forming a contact hole by a conventional manufacturing step of a semiconductor device, a resist is required to be formed on almost entire surface of a substrate so as to be applied on a film other than an area in which a contact hole is to be formed, leading ... 08/04/05 - 20050170642 - Methods for improving metal-to-metal contact in a via, devices made according to the methods, and systems including the same In damascene process integration, a reducing plasma is applied after the etch stop or barrier layer is opened over a copper layer. Currently known methods for opening barrier layers suffer from the disadvantage that they cause at least some of the underlying copper to oxidize to copper oxide.. Because copper ... 07/28/05 - 20050164494 - Method for forming semiconductor device A method for forming a semiconductor device includes the steps of forming a flowable film made of an insulating material with flowability; forming a first concave portion in the flowable film through transfer of a convex portion of a pressing face of a pressing member by pressing the pressing member ... 07/28/05 - 20050164493 - Shared contact for high-density memory cell design A new method and structure is created for a multi-transistor SRAM device. Standard processing steps are followed for the creation of CMOS devices of providing a patterned layer of gate material, of performing LDD impurity implants, of creating gate spacers. After the creation of the gate spacers, a new step ... 07/28/05 - 20050164492 - Method of manufacturing flexible wiring board In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer ... 07/28/05 - 20050164491 - Bit line contact hole and method for forming the same A method of forming a bit line contact hole. After transistors are formed on a substrate, a polysilicon layer conformally covers the transistors and the substrate. The polysilicon layer is defined to form an inner landing pad connecting with a doped region. A passivation layer is formed on the inner ... 07/21/05 - 20050158989 - Method of forming wiring and method of manufacturing image display system by using the same A method for forming via holes includes placing an insulating layer on a first wiring layer, forming opening portions in the insulating layer, and forming a second wiring layer on the insulating layer. At the time of forming the opening portions, the insulating layer is irradiated with a laser beam ... 07/21/05 - 20050158988 - Fabrication method for arranging ultra-fine particles A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and ... 07/14/05 - 20050153540 - Method of forming contact hole and method of manufacturing semiconductor device A method of forming a contact hole on a substrate by using a projection aligner comprising a lighting system including a light source, an aperture, and a condenser lens, a photo mask on which light from the lighting system is incident, and a projection lens for projecting the light from ... 07/07/05 - 20050148171 - Method for filling trench and relief geometries in semiconductor structures A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is ... 07/07/05 - 20050148170 - Developer-soluble materials and methods of using the same in via-first dual damascene applications Wet-recess (develop) gap-fill and bottom anti-reflective coatings based on a polyamic acid or polyester platform are provided. The polyamic acid platform allows imidization to form a polyimide when supplied with thermal energy. The gap-fill and bottom anti-reflective coatings are soluble in standard aqueous developers, and are useful for patterning via ... 07/07/05 - 20050148169 - Solvent vapor-assisted plasticization of photoresist films to achieve critical dimension reduction during temperature reflow The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The post exposure ... 07/07/05 - 20050148168 - Method for fabricating a through hole on a semiconductor substrate A method for fabricating a through hole is disclosed. First, a conductive structure having a conductive layer and a cap layer are formed on a substrate. A patterned first photoresist layer is formed on the substrate and the conductive structure to define a pattern of the through hole. Then, a ... 06/30/05 - 20050142856 - Method of fabricating interconnection structure of semiconductor device A method of fabricating an interconnection structure of a semiconductor device includes the steps of successively depositing an etch-stop layer and an intermetal insulating layer on a semiconductor substrate, forming a sacrificial insulating layer on the intermetal insulating layer, forming a photoresist pattern on the sacrificial insulating layer to define ... 06/30/05 - 20050142855 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device which, on performing a via first Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole. The method typically includes the steps of forming a bottom anti-reflective coating (BARC) in a via hole ... 06/23/05 - 20050136650 - Method of manufacturing semiconductor integrated circuit A method of manufacturing a semiconductor integrated circuit comprising a step of forming a lower-layer wiring, a step of forming a first viahole at a first cross point at which the lower-layer wiring and an upper-layer wiring intersect with each other in a plurality of cross points of a viahole-formation ... 06/23/05 - 20050136649 - Method and fabricating semiconductor device A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on ... 06/23/05 - 20050136648 - Method and system for forming a contact in a thin-film device An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, depositing a dielectric material, planarizing the dielectric material thereby exposing ... 06/16/05 - 20050130413 - Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of ... 06/16/05 - 20050130412 - Method for forming metal contact in semiconductor device A method for forming a metal contact in a semiconductor device includes the steps of: forming a bottom wire connected with a metal wire on a substrate; forming an inter-layer insulation layer on an entire surface of a substrate substructure including the bottom wire and the substrate; forming a metal ... 06/16/05 - 20050130411 - Method for forming openings in low-k dielectric layers A method for etching contact/via openings in low-k dielectric layers is described. The method introduces a carbon deficient ARL which is compatible with the acidic photoresists used by DUV photolithography. The carbon deficiency of the ARL permits the use of fluorocarbon plasma etching ambients to etch the openings in the ... 06/16/05 - 20050130410 - Contact hole printing by packing and unpacking A method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to ... 06/02/05 - 20050118801 - Technique for forming a gate electrode by using a hard mask The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical ... ### FreshPatents.com Support |