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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Contacting Multiple Semiconductive Regions (i.e., Interconnects) > Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization)Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087559 - Semiconductor device manufacturing method A semiconductor device manufacturing method is provided which is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. A gate electrode and a resistive interconnection are formed on a substrate and impurity ions are implanted into the surface of the substrate to ... 04/19/07 - 20070087558 - Semiconductor device having isolation pattern in interlayer insulating layer between capacitor contact plugs and methods of fabricating the same A semiconductor device having an isolation pattern inside an interlayer insulating layer between capacitor contact plugs and methods of fabrication the same: The semiconductor device includes an interlayer insulating layer covering a semiconductor substrate. At least two contact plugs passing the interlayer insulating layer and connected to the semiconductor substrate. ... 04/19/07 - 20070087557 - Semiconductor device with a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited ... 04/12/07 - 20070082477 - Integrated circuit fabricating techniques employing sacrificial liners The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via ... 04/05/07 - 20070077751 - Method of restoring low-k material or porous low-k layer A method of restoring a low-k material is described, applied to a substrate with a low-k material thereon, wherein the substrate has been subject to a previous process that raised the k-value of the low-k material. The method includes performing a plasma treatment to the low-k material to decrease the ... 03/29/07 - 20070072410 - Method of forming copper interconnection using dual damascene process Disclosed is a method of forming a copper interconnection using a dual damascene process. The method generally prevents formation of an undeveloped photoresist caused by the topology between a via hole and a trench and reduces or prevents defects in the copper interconnection, such as disconnection, via holes or voids. ... 03/29/07 - 20070072409 - Reflector with non-uniform metal oxide layer surface A reflector includes a non-uniform metal oxide layer surface. ... 03/15/07 - 20070059920 - Method of fabricating copper damascene and dual damascene interconnect wiring An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual ... 03/01/07 - 20070049005 - Method for forming dual damascene pattern in semiconductor manufacturing process A method for forming a dual damascene structure in a semiconductor manufacturing process is provided. The method includes forming a first dielectric layer and a first conductive layer on a semiconductor substrate; forming a second dielectric layer on the first conductive layer; applying a photoresist on the second dielectric layer; ... 02/22/07 - 20070042597 - Method for manufacturing semiconductor device It is an object of the present invention to provide a method for manufacturing a semiconductor device in which prevention of disconnection due to a step caused by a surface shape before film formation, control of increase in the cost in forming an insulating film over a large-sized substrate, improvement ... 02/22/07 - 20070042596 - Method of forming an interconnect structure for a semiconductor device A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the ... 02/15/07 - 20070037382 - Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof A semiconductor device includes an interconnection structure in which via-plug density is higher in an upper layer part than a lower layer part, wherein the peeling of the lower via-plugs at the time of formation of the upper-via-plugs is avoided by restricting the density of the upper s, defined for ... 02/15/07 - 20070037381 - Method for fabricating al metal line Disclosed is a method for fabricating an Al metal line. The method includes forming an insulating layer on a semiconductor substrate; forming a Ti layer, a bottom TiN layer, an Al layer and a top TiN layer in successive order on the insulating layer; plasma-treating the top TiN layer; forming ... 02/08/07 - 20070032068 - Semiconductor device and method for fabricating the same A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm and formed on a ... 02/08/07 - 20070032067 - Semiconductor device and method of manufacturing the same There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than ... 02/01/07 - 20070026664 - Semiconductor device and a method of manufacturing the same In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu ... 01/25/07 - 20070020917 - Methods for forming macroporous monolithic methylsilsesquioxanes The present invention relates to a two-step method of preparing methylsilsequixane (MSQ) materials suitable for chromatographic applications comprising treating a MSQ precursor with a suitable acid followed by treatment with a suitable base under conditions to form a MSQ monolith suitable for chromatographic applications. ... 01/25/07 - 20070020916 - Methods for forming flexible column die interconnects and resulting structures A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they ... 01/25/07 - 20070020915 - Mmic having back-side multi-layer signal routing A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate ... 01/18/07 - 20070015354 - Method for manufacturing electronic device and electronic device A method for manufacturing an electronic device comprises a step for forming a coating film (100) on a surface of a conductor portion-containing body (500), a step for forming a photosensitive film (110) on the conductor (500) on which the coating film (100) has been formed, a step for exposing ... 01/11/07 - 20070010087 - Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the ... 01/11/07 - 20070010086 - Circuit board with a through hole wire and manufacturing method thereof An aluminum substrate is drilled to form a first through hole, and is then laminated with copper foils on upper and lower surfaces of the aluminum substrate via a binder. Due to the pressure of the lamination, the binder is partially forced to flow into and fill the first through ... 01/11/07 - 20070010085 - Semiconductor device and fabrication method thereof Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric ... 01/04/07 - 20070004192 - Metal interconnection of a semiconductor device and method of fabricating the same Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and ... 12/28/06 - 20060292858 - Techniques to create low k ild for beol One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. ... 12/28/06 - 20060292857 - Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance ... 12/28/06 - 20060292856 - Method of patterning a porous dielectric material A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other ... 12/28/06 - 20060292855 - Current-aligned auto-generated non-equiaxial hole shape for wiring A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis. One aspect of the ... 12/28/06 - 20060292854 - Manufacturing method of dual damascene structure A manufacturing method of a dual damascene structure is provided. First, a barrier layer, a first dielectric layer, a second dielectric layer, a cap layer, a metal-containing hard mask layer, a dielectric hard mask layer, a first bottom anti-reflection coating (BARC) layer and a first photoresist layer are sequentially formed ... 12/28/06 - 20060292853 - Method for fabricating an integrated semiconductor circuit and semiconductor circuit The present invention relates to a method for fabricating an integrated semiconductor circuit having a conductor structure buried in a semiconductor substrate, and to an integrated semiconductor circuit, in which case the integrated semiconductor circuit may be an application specific semiconductor circuit or a semiconductor circuit that can be adapted ... 12/21/06 - 20060286792 - Dual damascene process A dual damascene process for fabricating a semiconductor device. A dielectric layer is formed on a substrate, comprising at least one via opening therein. A trench opening is formed in the dielectric layer above the via opening and the via opening widened by in-situ etching. ... 12/14/06 - 20060281300 - Semiconductor substrate and method of fabricating semiconductor device A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second ... 12/14/06 - 20060281299 - Method of fabricating silicon carbide-capped copper damascene interconnect A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of ... 12/14/06 - 20060281298 - Semiconductor device and manufacturing method of the same In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming ... 12/14/06 - 20060281297 - Multilayer electronic part and structure for mounting multilayer electronic part A multilayer electronic component includes a multilayer substrate having a first main surface and a second main surface, a resin layer having a mounting surface and a contact surface bonded to the first main surface, a via conductor provided inside the resin layer, and an external terminal electrode disposed on ... 12/07/06 - 20060276027 - Interconnects with harmonized stress and methods for fabricating the same Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one ... 11/30/06 - 20060270212 - Method of forming bit line of flash memory device A method for forming a semiconductor device includes forming a plurality of drain contact holes in a first interlayer insulating layer provided over a semiconductor substrate. First metal material having a predetermined thickness is formed over the first interlayer insulating layer, the first metal material filling the drain contact holes. ... 11/30/06 - 20060270211 - Method of fabricating wiring board and method of fabricating semiconductor device A method of fabricating a wiring board characterized in comprising a first step of forming a first solder resist layer on a support board and forming a first opening portion at the first solder resist layer, a second step of forming an electrode at the first opening portion, a third ... 11/30/06 - 20060270210 - Waveguide integrated circuit An integrated circuit includes many metallization levels. A thick dielectric region is placed above at least two metallization levels and laterally neighboring two or more metallization levels. That part of the two metallization levels which lie beneath the dielectric region forms a screen. A conducting strip is placed on the ... 11/23/06 - 20060264030 - Wire structure and forming method of the same A wire structure, comprising: a first insulating layer having a lower layer trench formed in an outer surface thereof; a first diffusion preventing film formed on an inner surface of the lower layer trench; a lower layer wire filled in the lower layer trench through the first diffusion preventing film; ... 11/23/06 - 20060264029 - Low inductance via structures In one embodiment, a method for forming a semiconductor device, comprises forming a first aperture and a second aperture in a first surface of the substrate, the first and second apertures being coaxial; forming, in the first aperture, a first conductive path between the first surface of the substrate and ... 11/23/06 - 20060264028 - Energy beam treatment to improve the hermeticity of a hermetic layer The present invention provides a process for increasing the hermeticity of a hermetic layer, a method for manufacturing an interconnect structure, and a method for manufacturing an integrated circuit. The process for increasing the hermeticity of the hermetic layer, without limitation, includes providing a hermetic layer over a substrate (160), ... 11/16/06 - 20060258147 - Method of forming closed air gap interconnects and structures formed thereby A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a ... 11/02/06 - 20060246712 - Dual resistance heater for phase change devices and manufacturing method thereof A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, ... 11/02/06 - 20060246711 - Method of patterning a low-k dielectric using a hard mask By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes. ... 10/26/06 - 20060240660 - Semiconductor stucture and method of manufacturing the same A semiconductor structure for a substrate having electronic elements formed thereon. The semiconductor structure comprises a dielectric layer and a conductive stuffing material. The dielectric layer is located over the substrate. It should be noticed that the dielectric layer has a plurality of trenched and a border shape of each ... 10/19/06 - 20060234493 - Method of manufacturing a device, device, non-contact type card medium, and electronic equipment Wirings 2B1 are formed by application of heat treatment after an ink jet system is used to discharge a conductive liquid L onto a provisional substrate 5 having a predetermined repellent property, bonding an insulating layer 4B1 to the wirings 2B1 with an adhesive material 3B1 therebetween, peeling and removing ... 10/19/06 - 20060234492 - Methods of forming polysilicon-comprising plugs and methods of forming flash memory circuitry This invention includes methods of forming polysilicon-comprising plugs, and methods of forming FLASH memory circuitry. In one implementation, a method of forming a polysilicon-comprising plug, includes providing a substrate comprising an opening formed therein. Polysilicon is formed within the opening to less than fill the opening. The polysilicon within the ... 10/12/06 - 20060228879 - Thin film resistor head structure and method for reducing head resistivity variance A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over ... 10/05/06 - 20060223304 - Semiconductor device and pattern generating method A first dummy pattern is arranged in the region allowed to generate the first dummy pattern, after that, the second dummy pattern is generated in the region not allowed to generate the first dummy pattern but allowed to generate the second dummy pattern to thereby enable to arrange the dummy ... 10/05/06 - 20060223303 - Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes the step of forming a first insulating section with a protruding section on a semiconductor substrate, the step of forming a first conducting section on the first insulating section so as to pass on a surface of the protruding section, the step ... 10/05/06 - 20060223302 - Self-aligned contacts for transistors Self-aligned contacts for transistors and methods for fabricating the contacts are described. An etch resistant material is patterned to create an opening that resides above a transistor gate structure. A selective etch is performed through the opening that does not etch the transistor gate structure but does etch material that ... 09/28/06 - 20060216923 - Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature ... 08/24/06 - 20060189125 - Multilayer wiring substrate, and method of producing same A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up ... 08/24/06 - 20060189124 - Semiconductor device having a through contact through a housing composition and method for producing the same A semiconductor device includes a housing composition and a through contact extending through the housing composition. The through contact is provided in a contact hole formed through the housing composition and having an asymmetrical funnel form with at least two opposite inner wall sides oriented substantially perpendicular to the top ... 08/24/06 - 20060189123 - Etchant and method of etching A fine wiring line profile with satisfactory precision is formed from a multilayer film containing a first layer made of an aluminum alloy and a second layer formed thereon made of a molybdenum-niobium alloy, by simultaneously etching the two layers constituting the multilayer film through only one etching operation while ... 08/24/06 - 20060189122 - Method of forming isolated features of semiconductor devices A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an array of features ... 08/17/06 - 20060183316 - Method of providing printed circuit board with conductive holes and board resulting therefrom A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by ... 08/10/06 - 20060178002 - Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer Exemplary embodiments of the invention generally include methods for forming multilayer metal interconnect structures using dual damascene methods that incorporate a via capping process to protect lower interconnection lines from etching damage or oxidation, for example, that may be caused by inadvertent exposure of lower interconnection lines to etching atmospheres. ... 07/27/06 - 20060166481 - Method of forming metal layer pattern and method of manufacturing image sensor using the same A method of forming a metal layer pattern comprises forming an interlayer insulating layer on a semiconductor substrate, forming a metal layer on the interlayer insulating layer, forming a mask pattern to expose a predetermined area of the metal layer, and forming a metal layer pattern by dry etching the ... 07/20/06 - 20060160352 - Method of forming interconnection in semiconductor device A multilayer interconnection structure is formed by a method comprising the steps of: Forming a low dielectric constant film on a substrate, curing the low dielectric constant film by irradiating it with UV light, laminating a UV blocking film, laminating a next low dielectric constant film, and curing the next ... 07/13/06 - 20060154473 - Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a ... 07/13/06 - 20060154472 - Etching method, program, computer readable storage medium and plasma processing apparatus A difference in etching rate between the coated silicon based insulating film and any of other kinds of silicon-based insulating films is reduced by using nitrogen gas as a part of the etching gas. Therefore, the underlying film may not be exposed to the etching gas for a long time, ... 07/06/06 - 20060148236 - Semiconductor device with a metal line and method of forming the same A semiconductor device with a metal line and a method of forming the same. The method includes forming an insulation layer on a semiconductor substrate including a predetermined lower structure, forming a vertical hole and a horizontal hole by etching the insulation layer, forming a supporting part by filling the ... 06/29/06 - 20060141765 - Metal wiring pattern for memory devices A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on ... 06/29/06 - 20060141764 - Method of manufacturing wiring board A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected ... 06/29/06 - 20060141763 - System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) ... 06/29/06 - 20060141762 - Interlocking via for package via integrity A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric ... 06/29/06 - 20060141761 - System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its ... 06/08/06 - 20060121722 - Method of making printed circuit board with varying depth conductive holes adapted for receiving pinned electrical components A method of making a printed circuit board in which openings of different length are formed using a cover atop one of the openings to prevent dielectric material from an interim layer of heat-deformable dielectric material from entering the opening when the sub-composite having the opening therein is bonded to ... 06/01/06 - 20060115977 - Method for forming metal wiring in semiconductor device Disclosed is a method for forming a metal wiring in a semiconductor device in order to improve the operational speed of the semiconductor device. The method includes the steps of depositing an interlayer dielectric film on a silicon substrate, in which the interlayer dielectric film has a contact hole for ... 05/25/06 - 20060110911 - Controlled electroless plating An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine ... 05/18/06 - 20060105564 - Method and system for reducing inter-layer capacitance in integrated circuits The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. ... 05/18/06 - 20060105563 - Method of forming a semiconductor device A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The ... 05/11/06 - 20060099798 - Semiconductor device and manufacturing method of the same Disclosed is a method of manufacturing a semiconductor device, including the steps of: forming on a second insulating film a first resist pattern having a first window; employing the first resist pattern as an etching mask to form first openings exposed from contact regions CR; forming, on a second conductive ... 05/04/06 - 20060094228 - Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits A metal structure for a contact pad of an integrated circuit (IC), which has copper interconnecting metallization (311). A portion (301) of this metallization is exposed to provide a contact pad to the IC. A conductive barrier layer (330) is positioned on the exposed portion o the copper metallization. A ... 04/27/06 - 20060088994 - Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of the metal layer is exposed at the edge ... 04/06/06 - 20060073696 - Semiconductor device and manufacturing method thereof A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the ... 03/30/06 - 20060068582 - Method for decreasing impedance of a power source in a printed circuit board A method for decreasing impedance of a power source in a printed circuit board includes: (a) forming a first metal plane over a first layer of the printed circuit board; (b) forming a second metal plane and a third metal plane over a second layer of the printed circuit board; ... 03/30/06 - 20060068581 - Method of forming via hole in resin layer To reliably expose an underlying layer at a bottom surface of a via hole to form a via hole even at a resin layer including an inorganic filler. A method of forming a via hole by firing a laser beam at a resin layer (10) including an inorganic filler (12) ... 03/23/06 - 20060063374 - Post passivation interconnection schemes on top of the ic chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick ... 03/23/06 - 20060063373 - Method of fabricating copper damascene and dual damascene interconnect wiring An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual ... 03/16/06 - 20060057836 - Method of stacking thin substrates by transfer bonding This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on ... 03/09/06 - 20060051955 - Top layers of metal for high performance ic's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within ... 03/02/06 - 20060046465 - Method for manufacturing a semiconductor device An increase in parasitic capacitance between lines, an increase of contact resistance, and corrosion of a metal line may be effectively reduced or prevented when a semiconductor device is manufactured by a method including forming an interlayer insulating layer including a low-k dielectric material on a semiconductor substrate having a ... 03/02/06 - 20060046464 - Wiring substrate and semiconductor device using the same A wiring substrate provides an inner wiring substrate having through hole portions. On at least one main surface of the inner wiring substrate, a plurality of build up layers are laminated. The build up layers have a stacked via, for example, as a power source system via. The stacked via ... 03/02/06 - 20060046463 - Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate underlying the conductive element. The through ... 02/16/06 - 20060035456 - Method and apparatus for deep sub-micron design of integrated circuits A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC ... 02/09/06 - 20060030144 - Method of fabricating integrated circuitry The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) ... 02/09/06 - 20060030143 - Barrier layer configurations and methods for processing microelectronic topographies having barrier layers A microelectronic topography includes a dielectric layer (DL) with a surface higher than an adjacent bulk metal feature (BMF) and further includes a barrier layer (BL) upon the BMF and extending higher than the DL. Another microelectronic topography includes a BL with a metal-oxide layer having a metal element concentration ... 02/02/06 - 20060024949 - Method of manufacturing semiconductor device The invention is directed to improvement of reliability of a process of separating a layer to be patterned such as a wiring layer in a semiconductor device manufacturing method. A wiring layer is formed on a back surface of a semiconductor substrate including an opening. A third resist layer (positive ... 02/02/06 - 20060024948 - Method of fabricating dual damascene interconnection In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer ... 02/02/06 - 20060024947 - Electronic component comprising predominantly organic functional materials and a method for the production thereof Electronic component comprising predominantly organic functional materials and a process for the production thereof. The invention concerns an electronic component comprising predominantly organic functional materials with improved through-plating. The through-plating is formed in the present case prior to application of the insulating layer, in the form of a free-standing raised ... 02/02/06 - 20060024946 - Method for filling a contact hole and integrated circuit arrangement with contact hole A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple ... 01/19/06 - 20060014376 - Stacked via-stud with improved reliability in copper metallurgy A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of ... 01/19/06 - 20060014375 - Soluble carbon nanotubes A method of solubilizing carbon nanotubes. Carbon nanotubes, and urea are mixed together and then heated. ... 01/19/06 - 20060014374 - Layer assembly and method for producing a layer assembly The invention relates to a layer arrangement and to a process for producing a layer arrangement. The layer arrangement has a layer which is arranged on a substrate and includes a first subregion comprising decomposable material and a second subregion which is arranged next to the first subregion and has ... 01/12/06 - 20060009026 - Method of fabricating wiring board In a wiring board fabrication method including a wiring formation process using a damascene method, via holes reaching an underlying wiring layer are formed in an interlayer insulating layer formed on the underlying wiring layer, smears caused at that time are removed, and then a photosensitive permanent resist layer is ... 01/05/06 - 20060003572 - Method for improving a semiconductor device delamination resistance A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer ... 12/29/05 - 20050287790 - Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of ... 12/29/05 - 20050287789 - Substrate with patterned conductive layer A method of processing a substrate is provided. The method includes providing a substrate having a first surface, a second surface, and conductive paths extending from the first surface to the second surface. The method also includes (1) covering a portion of the first surface with a conductive material, and ... 12/22/05 - 20050282378 - Interconnects forming method and interconnects forming apparatus An interconnects forming method and an interconnects forming apparatus are useful for embedding a conductive material (interconnect material), such as copper or silver, into interconnect recesses provided in a surface of a substrate, such as a semiconductor wafer, to thereby form embedded interconnects, and selectively covering the surfaces of embedded ... 12/08/05 - 20050272251 - Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of ... 12/08/05 - 20050272250 - Method of forming self-aligned contact and method of manufacturing semiconductor memory device by using the same In an embodiment a method of forming self-aligned contacts in a semiconductor memory device includes: forming conductive stacks of conductive layers on a semiconductor substrate; forming insulating spacer layers on sidewalls of the conductive stacks; forming an insulating layer; forming a capping insulating layer covering portions of the insulating layer; ... 12/08/05 - 20050272249 - Method and system for producing conductive patterns on a substrate A method of producing a conductive pattern on a substrate, including the steps of providing a surface of the substrate with a conductive layer, which is formed by providing the surface of the substrate at least partly with conductive particles, by directly using the adhesive power of the surface of ... 12/01/05 - 20050266675 - Wafer-level thick film standing-wave clocking An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to ... 11/24/05 - 20050260846 - Substrate processing method, semiconductor device production method, and semiconductor device A substrate processing method is disclosed that, when forming a copper film on a miniaturized pattern with a copper diffusion prevention film being formed thereon, allows cleaning the copper diffusion prevention film on a substrate by using a supercritical medium, and allows the copper film to be formed by using ... 11/24/05 - 20050260845 - Low-k dielectric etch process for dual-damascene structures A method includes performing a first etch process to form a via hole in a dual-damascene integrated circuit structure comprising a first dielectric layer and a second dielectric layer. The via hole extends at least substantially through the first and second dielectric layers. The method further includes filling at least ... 11/17/05 - 20050255687 - Plasma treatment for silicon-based dielectrics An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist ... 11/10/05 - 20050250310 - Multi-layer interconnection circuit module and manufacturing method thereof The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers (8) to (12) are adapted so that photo-lithographic processing ... 10/20/05 - 20050233575 - Semiconductor device and manufacturing method thereof, integrated circuit, electro-optic device, and electronic equipment Exemplary embodiments of the invention provide techniques that enable avoidance of the concentration of an electric field at the edge of a semiconductor film in a semiconductor device such as a thin film transistor, thereby enhancing the reliability. Exemplary embodiments provide a method of manufacturing a semiconductor device using a ... 10/13/05 - 20050227477 - Method for fabricating semiconductor device and acceleration sensor An object of the present invention is to provide a technique for reducing a step height to be covered by photoresist during formation of an electrode connected to a semiconductor substrate, e.g. a silicon substrate on which an acceleration sensor resides. In order to achieve this object, an opening (80) ... 10/06/05 - 20050221604 - Interconnect structure for an integrated circuit and method of fabrication An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric. ... 10/06/05 - 20050221603 - System architecture of semiconductor manufacturing equipment Provided herein is a system architecture of semiconductor manufacturing equipment, wherein degas chamber(s) are integrated to the conventional pass-through chamber location. Also provided herein is a system/method for depositing Cu barrier and seed layers on a semiconductor wafer. This system comprises a front opening unified pod(s), a single wafer loadlock ... 10/06/05 - 20050221602 - Electrodepositing a metal in integrated circuit applications A method is described in which a contact hole (18) to an interconnect (14) in an insulating layer (16) is fabricated. A barrier layer (20) is subsequently applied. Afterward, a photoresist layer (30) is applied, irradiated and developed. With the aid of a galvanic method, a copper contact (32) is ... 10/06/05 - 20050221601 - Semiconductor device and method for manufacturing the same A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter ... 10/06/05 - 20050221600 - Method of manufacturing a semiconductor device having damascene structures with air gaps A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level ... 09/29/05 - 20050215050 - Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in ... 09/29/05 - 20050215049 - Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) forming a catalyst layer on the growth mode control layer, ... 09/29/05 - 20050215048 - Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits A metal structure for a contact pad of an integrated circuit (IC), which has copper interconnecting metallization (311). A portion (301) of this metallization is exposed to provide a contact pad to the IC. A conductive barrier layer (330) is positioned on the exposed portion of the copper metallization. A ... 09/22/05 - 20050208757 - Top layers of metal for high performance ic's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a ... 09/22/05 - 20050208756 - Method of removing resist, semiconductor device thereby and method of manufacturing a semiconductor device Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is ... 09/22/05 - 20050208755 - Nitrogen-free arc layer and a method of manufacturing the same The present invention provides a nitrogen-free ARC layer, which is formed on the basis of silane and carbon dioxide by PECVD in a nitrogen-free deposition atmosphere. The optical characteristics may be tuned in a wide range, wherein, in particular, a back reflection into the resist is maintained at 3% or ... 09/22/05 - 20050208754 - Method of growing electrical conductors A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a gaseous inorganic reducing ... 09/15/05 - 20050202667 - Electrochemical fabrication methods incorporating dielectric materials and/or using dielectric substrates Various embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer. In other embodiments, electrochemically ... 09/08/05 - 20050196954 - Method for manufacturing semiconductor integrated circuit device Provided is a manufacturing method of a semiconductor device which comprises (a) depositing a first insulating film over a wafer, (b) forming an interconnect opening in the first insulating film, (c) forming, in the interconnect opening, an interconnect having a conductor film comprised mainly of copper, (d) forming a taper ... 09/08/05 - 20050196953 - Method for forming wiring of semiconductor device According to the present invention, a connection hole is formed above a substrate by an etching treatment using a first resist film as a mask, and after the first resist film is removed by stripping, the substrate is exposed to a water vapor atmosphere. Thus, an amine component in the ... 09/08/05 - 20050196952 - Method for production of a semiconductor structure A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring ... 09/08/05 - 20050196951 - Method of forming dual damascene structures A method of forming at least one wire on a substrate comprising at least one conductive region is provided. AnAn insulatingayer is disposed on the substrate. The method includes forming a hard mask layer on the insulating layer followed by forming at least one recess by removing portions of the ... 09/08/05 - 20050196950 - Method of producing layered assembly and a layered assembly An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, ... 09/01/05 - 20050191845 - Semiconductor device having a guard ring A semiconductor device has a guard ring in a multilayer interconnection structure, wherein the guard ring includes a conductive wall extending zigzag in a plane parallel with a principal surface of a substrate. ... 09/01/05 - 20050191844 - Low capacitance wiring layout and method for making same Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than ... 09/01/05 - 20050191843 - Fabrication method for semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently The present invention provides a fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently. A fabrication of a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the ... 09/01/05 - 20050191842 - High-aspect-ratio metal-polymer composite structures for nano interconnects A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were ... 08/25/05 - 20050186775 - Conducting wire and contact opening forming method for reducing photoresist thickness and via resistance Disclosed is a method for forming conducting wire and contact opening in a semiconductor device. The method of the present invention utilizes the formation of metal regions as a mask for etching a conductive layer of the semiconductor device to remove unnecessary portions so as to form conducting wires. The ... 08/04/05 - 20050170636 - Production method of semiconductor device The method includes a step of forming on an underlayer wiring a first insulating film, a second insulating, and first mask forming layer; a step of forming a first resist mask (20) having an inverted pattern of wiring trenches for the upper wiring; a step of etching the first mask ... 08/04/05 - 20050170635 - Semiconductor device and manufacturing method thereof A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding ... 08/04/05 - 20050170634 - High performance system-on-chip discrete components using post passivation process A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. ... 08/04/05 - 20050170633 - Semiconductor device and method of manufacturing a semiconductor device A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC ... 08/04/05 - 20050170632 - Methods of manufacturing multi-level metal lines in semiconductor devices Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and second metal layers; forming first and second metal layer pattern by ... 07/28/05 - 20050164489 - Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is ... 07/28/05 - 20050164488 - Method of fabricating a plurality of ferroelectric capacitors In one embodiment, a plurality of bottom electrodes spaced apart from each other are formed on a lower insulating layer. A high-k dielectric layer and an upper conductive layer are sequentially and conformally formed overlying the bottom electrodes. The high-k dielectric layer and the upper conductive layer cover the bottom ... 07/21/05 - 20050158982 - Semiconductor device manufacturing method A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern in the third mask layer; selectively processing the third mask ... 07/14/05 - 20050153536 - Method for manufacturing semiconductor device A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film ... 07/14/05 - 20050153535 - Method for forming contact in semiconductor device Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard ... 07/07/05 - 20050148166 - [structure applied to a photolithographic process and method for fabricating a semiconductor device] A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. ... 06/30/05 - 20050142846 - Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ... 06/30/05 - 20050142845 - Method of forming plug of semiconductor device A method for forming a plug of a semiconductor device according to a preferred embodiment includes forming a metal wiring on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate having the metal wiring, forming a contact hole for partially exposing the metal wiring by selectively etching ... 06/30/05 - 20050142844 - Method for fabricating metal interconnect in semiconductor device A method for fabricating a metal interconnect in a semiconductor device is disclosed. A disclosed method comprises: forming a via hole by a damascene process in an interlayer dielectric layer on a substrate; depositing a conducting layer on the substrate including the via hole; forming a photoresist pattern on the ... 06/30/05 - 20050142843 - Method for forming metallic interconnects in semiconductor devices A method for forming a metallic interconnect in a semiconductor device is disclosed. An example method forms an IDL on a substrate including predetermined devices, forms a via hole in the IDL, depositing a first metal diffusion preventive layer and a metal layer to form a via plug on the ... 06/30/05 - 20050142842 - Method for forming metal wiring of semiconductor device A method for forming a metal wiring of a semiconductor includes forming an inter metal dielectric layer on a semiconductor substrate having a predetermined low structure with a conductive layer. A plurality of contact holes is formed to expose the conductive layer through the inter metal dielectric layer. A first ... 06/30/05 - 20050142841 - Method for forming metal pattern to reduce contact resistivity with interconnection contact A method for forming a metal pattern in a semiconductor device which is capable of reducing contact resistivity with an interconnection contact. The method includes forming a tungsten interconnection contact passing through a lower insulating layer on a semiconductor substrate, forming an upper insulating layer covering the interconnection contact, and ... 06/30/05 - 20050142840 - Semiconductor device having a multilevel interconnection and a method for manufacturing the same A semiconductor device having a multilevel interconnection encompasses (a) a subject level interconnect, (b) a subject interlevel insulator disposed on the subject level interconnect, (c) a connecting via-plug buried in the subject interlevel insulator, the bottom surface of the connecting via-plug is in contact with the subject level interconnect, (d) ... 06/23/05 - 20050136643 - Dielectric film forming method for semiconductor device and semiconductor device Aspects of the invention can provide semiconductor devices and dielectric film forming methods for semiconductor devices in which inter-wiring dielectric films can be formed only in fine gaps among wirings, and which does not have influences by absorption and discharge of gas and moisture from dielectric films and can be ... 06/23/05 - 20050136642 - Method for fabricating semiconductor device Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first ... 06/09/05 - 20050124150 - Method for fabricating semiconductor device The present invention relates to a semiconductor device fabrication method, which includes forming an inter metal dielectric on a semiconductor substrate having wirings and planarizing the inter metal dielectric through a chemical mechanical polishing, wherein the inter metal dielectric is formed by carrying out at least one cycle of depositing ... ### FreshPatents.com Support - Terms & Conditions |