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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Contacting Multiple Semiconductive Regions (i.e., Interconnects) > Forming Contacts Of Differing Depths Into Semiconductor Substrate Forming Contacts Of Differing Depths Into Semiconductor SubstrateForming Contacts Of Differing Depths Into Semiconductor Substrate patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/22/07 - 20070066048 - Method for creating electrically conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material ... 03/22/07 - 20070066047 - Method of forming opening and contact A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer. ... 02/01/07 - 20070026663 - A semiconductor device and method for manufacturing the semiconductor device A semiconductor device, comprises: a wiring formed on a first insulating film, a second insulating film formed on the first insulating film and on the wiring, a contact hole formed in the second insulating film and located on the wiring, a coating that covers a sidewall of the contact hole ... 10/26/06 - 20060240659 - Metal interconnection structure of a semiconductor device having low resistance and method of fabricating the same Provided is a metal interconnection structure of a semiconductor device, comprising a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and ... 09/07/06 - 20060199369 - Ribs for line collapse prevention in damascene structures A method of preventing resist line collapse in damascene structures and a structure thereof is disclosed. A damascene pattern for resist lines is enhanced with ribs extending therefrom. The ribs provide mechanical support for resist lines and improve the lithography process for forming the resist lines, particularly when a negative ... 02/16/06 - 20060035455 - Interconnect dielectric tuning An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all ... 12/22/05 - 20050282377 - Method of making a semiconductor device having improved contacts A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This ... 12/22/05 - 20050282376 - Method of making a semiconductor device having improved contacts A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This ... 12/22/05 - 20050282375 - Semiconductor device and manufacturing method thereof An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of ... 12/01/05 - 20050266674 - Screen printing method of forming conductive bumps A screen printing method of conductive material is applied to a wafer with a conductive surface thereon. A dielectric layer on the wafer exposes the conductive surface to a first opening. A mask formed on the dielectric layer has a plurality of second openings corresponding to the first opening. The ... 09/15/05 - 20050202666 - Method of fabricating semiconductor device A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in ... 07/21/05 - 20050158981 - Method of fabricating display panel First, a substrate with at least one thin film transistor is provided. A protection layer and a planarization layer are sequentially formed on the substrate. Then, the planarization layer is patterned and an opening is formed in the planarization above the thin film transistor. An etching process is performed by ... 06/30/05 - 20050142839 - Conductive layers and fabrication methods thereof Methods for forming conductive layers. A layer of metal composite is applied on a substrate, comprising a plurality of metal flakes, a plurality of nanometer metal spheres, and a plurality of mixed metal precursors. The plurality of mixed metal precursors comprises a mixture of inorganic salts and organic acidic salts. ... ### FreshPatents.com Support |