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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Contacting Multiple Semiconductive Regions (i.e., Interconnects) > Air Bridge Structure Air Bridge StructureAir Bridge Structure patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/08/07 - 20070054485 - Integration control and reliability enhancement of interconnect air cavities An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance ... 03/01/07 - 20070049004 - Semiconductor constructions, and methods of forming layers The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to ... 03/01/07 - 20070049003 - Semiconductor constructions and methods of forming layers The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to ... 02/15/07 - 20070037380 - Controlling lateral distribution of air gaps in interconnects Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect ... 12/28/06 - 20060292852 - Back end interconnect with a shaped interface An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner ... 11/23/06 - 20060264027 - Air gap interconnect structure and method thereof Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of ... 11/16/06 - 20060258146 - Integrated circuits having organic-inorganic dielectric materials and methods for forming such integrated circuits A method for making an integrated circuit. An area of dielectric material is formed on a substrate by hydrolyzing a plurality of precursors to form a hybrid organic inorganic material. One of the precursors is a compound R1R2R3SiR4, wherein R1, R2, R3 are each independently aryl, a cross linkable group, ... 09/07/06 - 20060199368 - Interconnect arrangement and associated production methods An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To ... 08/17/06 - 20060183315 - Method to create air gaps using non-plasma processes to damage ild materials A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be ... 07/06/06 - 20060148235 - Devices and methods of preventing plasma charging damage in semiconductor devices Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing ... 06/22/06 - 20060134906 - Post-esl porogen burn-out for copper elk integration A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene ... 04/20/06 - 20060084262 - Low-k dielectric process for multilevel interconnection using microcavity engineering during electric circuit manufacture One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form ... 04/06/06 - 20060073695 - Gas dielectric structure forming methods Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the ... 03/16/06 - 20060057835 - Air-gap insulated interconnections Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, ... 12/15/05 - 20050277284 - Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device includes forming first wirings assigned in a first region and second wirings assigned in a second region having a lower wiring density than the first region; covering the first and second wirings with a sacrificial film; reducing a thickness of the sacrificial film ... 10/06/05 - 20050221599 - Etching method, semiconductor and fabricating method for the same An organic/inorganic hybrid film represented by SiCxHyOz (x>0, y≧0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to ... 09/29/05 - 20050215047 - Method of manufacturing a semiconductor device having damascene structures with air gaps A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, ... 09/29/05 - 20050215046 - Electrochemical fabrication methods incorporating dielectric materials and/or using dielectric substrates Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials ... 09/22/05 - 20050208753 - Dual-damascene interconnects without an etch stop layer by alternating ilds A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low ... 09/22/05 - 20050208752 - Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the ... 09/01/05 - 20050191841 - Semiconductor device and wiring forming method in semiconductor device The present invention provides a semiconductor device in which a problem such as a thermal diffusion defect in a hollow wiring technique can be solved. In the semiconductor device, a gap is formed between wirings formed on a substrate, and the gap is filled with a gas having a thermal ... 08/18/05 - 20050181593 - Selectively converted inter-layer dielectric An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by ... ### FreshPatents.com Support |