REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
 
|
|
Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Contacting Multiple Semiconductive Regions (i.e., Interconnects) Contacting Multiple Semiconductive Regions (i.e., Interconnects)Contacting Multiple Semiconductive Regions (i.e., Interconnects) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087556 - Method and mesh reference structures for implementing z-axis cross-talk reduction through copper sputtering onto mesh reference planes A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh ... 04/19/07 - 20070087555 - Interconnection structure with low dielectric constant An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the ... 04/19/07 - 20070087554 - Interconnection structure with low dielectric constant A method for producing an interconnection structure including at least one insulating layer having a low dielectric constant and at least one metal connection element coated with a support layer and capable of connecting to at least one conductive area of a microelectronic device. The interconnection structure has an improved ... 04/12/07 - 20070082476 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such ... 04/05/07 - 20070077750 - Atomic layer deposition processes for ruthenium materials Embodiments of the invention provide a method for depositing ruthenium materials on a substrate by various vapor deposition processes, such as atomic layer deposition (ALD) and plasma-enhanced ALD (PE-ALD). In one aspect, the process has little or no initiation delay and maintains a fast deposition rate while forming a ruthenium ... 04/05/07 - 20070077749 - Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barrier layer By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickness of the titanium-based barrier layer ... 04/05/07 - 20070077748 - Method for forming a semiconductor product and semiconductor product A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged ... 04/05/07 - 20070077747 - Microelectronic package having multiple conductive paths through an opening in a support substrate Microelectronic packages are disclosed. A microelectronic package may include a substrate having first and second sides. Passive components may be located on the first side of the substrate. Interconnects may also be located on the first side of the substrate, and may be electrically coupled with the passive components. Microelectronic ... 03/29/07 - 20070072408 - Fabrication method of semiconductor integrated circuit device The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, ... 03/29/07 - 20070072407 - Method of fabricating self-aligned contact pad using chemical mechanical polishing process A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping ... 03/29/07 - 20070072406 - Methods of forming integrated circuit devices having metal interconnect structures therein Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first ... 03/15/07 - 20070059919 - Method of manufacturing semiconductor device Disclosed herein is a method of manufacturing a semiconductor device, including the steps of: forming an interlayer insulating film on a semiconductor substrate; forming a metal mask on the interlayer insulating film; forming a pattern trench in the metal mask and the interlayer insulating film by etching away parts of ... 03/15/07 - 20070059918 - Rigid-flexible printed circuit board for package on package and manufacturing method The present invention relates to a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a ... 02/15/07 - 20070037379 - 3d ic method and device A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to ... 02/01/07 - 20070026662 - Semiconductor device and method of manufacturing the same A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, ... 01/25/07 - 20070020914 - Circuit substrate and method of manufacturing the same In a method of manufacturing a circuit substrate of the present invention, a first through hole is formed in a semiconductor substrate and a first insulating layer is formed on the entire surface of the semiconductor substrate, and then first wiring layers connected to each other via an outer through ... 01/11/07 - 20070010084 - Semiconductor processing methods, and semiconductor constructions The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material ... 01/04/07 - 20070004191 - Novel techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on ... 12/28/06 - 20060292851 - Circuitry component and method for forming the same A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and ... 12/28/06 - 20060292850 - Method for manufacturing semiconductor device and non-volatile memory A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a ... 12/14/06 - 20060281296 - Routingless chip architecture A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back-end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the ... 12/14/06 - 20060281295 - Methods of manufacturing semiconductor devices and structures thereof Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating ... 12/07/06 - 20060276026 - Semiconductor device and method for fabricating the same A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land ... 12/07/06 - 20060276025 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprises forming a laser marking, forming a trench pattern, forming a metal interconnection layer, removing a predetermined portion of the metal interconnection layer, and planarizing the metal interconnection layer. The laser marking is formed in a first region of a wafer, and the ... 11/23/06 - 20060264026 - Dendrite growth control circuit A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is ... 11/23/06 - 20060264025 - Stacked semiconductor device and method of manufacturing the same In a stacked semiconductor device and method of manufacturing the same, an insulation multilayer pattern is formed on a substrate. The insulation multilayer pattern includes a first insulating interlayer pattern, a second insulating interlayer pattern and an opening exposing a surface of the substrate. A first channel pattern may be ... 11/16/06 - 20060258145 - Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device may involve providing a first insulation pattern on a substrate including first and second regions. The first insulation pattern may include a first contact hole for exposing the first region. A spacer may be provided on a sidewall of the first insulation pattern. ... 11/16/06 - 20060258144 - Method of forming metal interconnect for semiconductor device based on selective damascene process Provided is a method for forming metal interconnect only in desired regions of a semiconductor device based on selective damascene using an insulation material against plating to form the metal interconnect without a Chemical Mechanical Polishing (CMP) or an additional lithography process. The selective damascene is stable and effective in ... 11/16/06 - 20060258143 - Method of reducing process steps in metal line protective structure formation A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal line and forming a protective plate in the plate opening on the top metal line. ... 11/16/06 - 20060258142 - Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited ... 11/09/06 - 20060252252 - Electroless deposition processes and compositions for forming interconnects In one embodiment, a method for depositing a material on a substrate is provided which includes positioning a substrate containing a contact within a process chamber, exposing the substrate to at least one pretreatment step and depositing a fill the contact vias by an electroless deposition process. The pretreatment step ... 11/09/06 - 20060252251 - Method of growing carbon nanotubes and method of manufacturing field emission device having the same In a method of forming carbon nanotubes (CNTs) and a method of manufacturing a field emission display (FED) device using the CNTs, the method includes preparing a substrate on which a silicon layer is formed, sequentially forming a buffer layer and a catalyst metal layer on the silicon layer, partly ... 11/09/06 - 20060252250 - Method of fabricating a dual-damascene copper structure A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric layer, wherein a portion of the semiconductor substrate is exposed in the dual-damascene hole. A PVD process and an atomic CVD process are sequentially ... 11/02/06 - 20060246710 - Methods of fabricating semiconductor devices including contact plugs having laterally extending portions and related devices In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers ... 11/02/06 - 20060246709 - Methods of forming semiconductor devices having stacked transistors and related devices A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on ... 11/02/06 - 20060246708 - Method for fabricating semiconductor device with metal line A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in ... 11/02/06 - 20060246707 - Integrated circuit and method of manufacture An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second ... 10/05/06 - 20060223301 - Formation of deep via airgaps for three dimensional wafer to wafer interconnect A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the ... 10/05/06 - 20060223300 - Organometallic precursors for the chemical phase deposition of metal films in interconnect applications Chemical phase deposition processes utilizing organometallic precursors to form thin films are herein described. The organometallic precursors may include a single metal center or multiple metal centers. The chemical phase deposition may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or hybrid CVD and ALD. The use of these ... 09/28/06 - 20060216922 - Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature ... 09/28/06 - 20060216921 - Through conductor and its manufacturing method The present invention provides a through conductor comprising a conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is provided with a first conductor which extends in the direction of thickness of the silicon substrate from the upper surface of the ... 09/28/06 - 20060216920 - Method for fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive material in the first opening. Then form a second ... 09/21/06 - 20060211235 - Semiconductor device and manufacturing process therefor A semiconductor device 100 has a semiconductor substrate (not shown); a first interconnect 108 made of a copper-containing metal which is formed over the semiconductor substrate; a conductive first plug 114 formed over the first interconnect 108 and connected to the first interconnect 108; a Cu silicide layer 111 over ... 09/07/06 - 20060199367 - Semiconductor device and manufacturing method thereof A manufacturing method of interconnect is provided. A dielectric layer is provided. A metal layer is formed in the dielectric layer. A fluorine-containing barrier layer is formed on the dielectric layer and covers the metal layer. The fluorine-containing barrier layer is formed by using chemical deposition method and introducing fluorine ... 09/07/06 - 20060199366 - Reduced dry etching lag A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with ... 09/07/06 - 20060199365 - Junction-isolated vias A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other side are provided. The conductive via is junction-isolated from the bulk of the silicon substrate by diffusing the via ... 08/31/06 - 20060194426 - Method for manufacturing dual damascene structure with a trench formed first A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer ... 08/31/06 - 20060194425 - Anisotropic conductive adhesive, electrode connection structure and method using the adhesive Anisotropic conductive adhesive has conductive particles dispersed in adhesive and includes hard particles having conductivity, a resin layer that coats the hard particles and a conductive layer that coats the resin layer. A connection structure electrically connects electrodes to each other with the anisotropic conductive adhesive. A connection method includes ... 08/24/06 - 20060189121 - Thin silicon based substrate Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die. ... 08/24/06 - 20060189120 - Method of making reinforced semiconductor package A method of making a reinforced semiconductor package includes forming a semiconductor interconnect tablet (24). Formation of the tablet includes providing a plurality of conductive metal tabs (10), positioning a first end (12) of the tabs (10) in a first section of a mold chase (14), positioning a second section ... 08/17/06 - 20060183314 - Method for fabricating interconnect structures with reduced plasma damage Methods to form interconnect structures utilizing sacrificial filling material layers are described herein. Utilizing the sacrificial filling material makes it possible to reduce damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability. ... 08/10/06 - 20060178001 - Method for fabricating interconnection in an insulating layer on a wafer and structure thereof A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive ... 07/27/06 - 20060166480 - Interconnection of through-wafer vias using bridge structures Bridge structures provide a surface on which to form interconnections to components through through-hole vias. The bridge structures at least partially, and preferably fully, span the gap between two wafers, and, more specifically, between a through-hole via in one wafer and a corresponding component on the other wafer. Bridge structure ... 07/27/06 - 20060166479 - Interconnection device for a printed circuit board, a method of manufacturing the same, and an interconnection assembly having the same The present invention relates to an interconnect device for a printed circuit board, a method of manufacturing the same and an inter-connect assembly having the same. According to one aspect of the present invention, the interconnect device for a printed circuit board comprises: a first contact section 10 having a ... 07/20/06 - 20060160351 - Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the ... 07/20/06 - 20060160350 - On-chip cu interconnection using 1 to 5 nm thick metal cap Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion ... 07/20/06 - 20060160349 - Interconnect structures with encasing cap and methods of making thereof A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure. ... 07/13/06 - 20060154471 - Dual damascene interconnections having low k layer with reduced damage arising from photoresist stripping A method and apparatus is provided for fabricating a dual damascene interconnection. The method begins by forming on a substrate a dielectric layer that includes an organosilicon material, forming a via photoresist pattern over the dielectric layer, and etching a via in the dielectric layer using the via photoresist pattern ... 07/13/06 - 20060154470 - Integrated circuit having structural support for a flip-chip interconnect pad and method therefor A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more ... 07/13/06 - 20060154469 - Method and apparatus for providing structural support for interconnect pad while allowing signal conductance A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the ... 07/06/06 - 20060148234 - Non-via method of connecting magnetoelectric elements with conductive line A non-via method of connecting a magnetoelectric element with a conductive line. A magnetoelectric element is formed on a substrate, and spacers are formed on side walls of the magnetoelectric element. A dielectric layer is deposited over the substrate and magnetoelectric element and planarized to a level above the magnetoelectric ... 06/22/06 - 20060134905 - Multilevel fabrication processing by functional regrouping of material deposition, lithography, and etching A method of multilevel microfabrication processing is provided. The method includes providing a planar substrate that comprises one or more material layers. A first hardmask layer placed on top of the substrate is patterned into the lithographic pattern desired for the top lithographic layer. Subsequent hardmask layers are patterned until ... 06/22/06 - 20060134904 - Microelecromechanical system microphone fabrication including signal processing circuitry on common substrate A MEMS microphone is formed on a single substrate that also includes microelectronic circuitry. High-temperature tolerance metals are used to form contacts in a metallization step before performing deep reactive ion etching and back patterning steps to form a MEMS microphone. High-temperature tolerant metals such as titanium, tungsten, chromium, etc. ... 06/15/06 - 20060128137 - Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill ... 06/08/06 - 20060121721 - Methods for forming dual damascene wiring using porogen containing sacrificial via filler material Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer dielectric layer such that the sacrificial material can be transformed to porous material that can be quickly and efficiently removed from ... 06/08/06 - 20060121720 - Low stress semiconductor device coating and method of forming thereof A low stress, protective coating for a semiconductor device and a method for its manufacture. A preferred embodiment comprises coating the top surface of a semiconductor die with polyimide except for corner regions of the die. Not having corners in the polyimide protective overcoat generally reduces shear stresses in the ... 06/01/06 - 20060115976 - Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is ... 05/25/06 - 20060110909 - Dendrite growth control circuit A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is ... 05/18/06 - 20060105562 - Method to make nano structure below 25 nanometer with high uniformity on large scale A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques. ... 05/18/06 - 20060105561 - Method of manufacturing a self-aligned contact structure The present invention provides a method of manufacturing a self-aligned contact structure comprising a semiconductor substrate having at least two gate stack structures formed thereon. A dielectric layer is formed over the gate stack structures. Each gate stack structure has a nitride layer surface. A portion of the dielectric layer ... 05/11/06 - 20060099797 - Integrated circuits with contemporaneously formed array electrodes and logic interconnects The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting ... 05/11/06 - 20060099796 - Method of forming a multi-layer semiconductor structure having a seam-less bonding interface A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined ... 05/11/06 - 20060099795 - I-shaped and l-shaped contact structures and their fabrication methods Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the ... 05/11/06 - 20060099794 - Interconnect structure to reduce stress induced voiding effect An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce ... 05/11/06 - 20060099793 - Contact for dual liner product A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and ... 05/04/06 - 20060094227 - Method of forming a contact in a semiconductor device Deterioration of yield may be prevented when a contact in a semiconductor device is made by a method including forming a contact hole by selectively removing an insulating layer from a semiconductor substrate, depositing a barrier layer on the insulating layer and on the surface of (or in) the contact ... 04/27/06 - 20060088993 - Iridium oxide nanostructure patterning A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas ... 04/20/06 - 20060084261 - Interconnect layout method An interconnect layout method capable of reducing variations in shape of gate patterns and improving yield of a semiconductor device is provided. In an interconnect layout 100, the first gate pattern, the second gate pattern, the first dummy pattern, and the second dummy pattern are arranged so that, if a ... 04/20/06 - 20060084260 - Copper processing using an ozone-solvent solution The present invention relates to a method and apparatus for treating materials such as copper or copper based metal alloys, used in fabricating semiconductor devices with an ozone solvent solution and avoiding damage to metals by corrosion. The invention is also applicable to treating of materials such as copper and ... 04/13/06 - 20060079081 - Method for fabricating electrical connection structure of circuit board A method for fabricating an electrical connection structure of a circuit board is proposed. A patterned resist layer is formed on the circuit board having a plurality of conductive pads, and a plurality of openings is formed in the resist layer to expose the conductive pads. A first conductive material ... 04/13/06 - 20060079080 - Method of providing contact via to a surface A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an ... 04/13/06 - 20060079079 - Method of manufacturing of thin based substrate Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die. ... 04/06/06 - 20060073694 - Method for isolating semiconductor device structures and structures thereof An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry. The removal of interconnecting diffusion region portions and gate electrode portions can be performed sequentially, at substantially ... 03/23/06 - 20060063372 - Semiconductor device and manufacturing method thereof An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole ... 03/23/06 - 20060063371 - Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses ... 03/23/06 - 20060063370 - Semiconductor device interconnect fabricating techniques The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively ... 03/23/06 - 20060063369 - Sub-resolution gaps generated by controlled over-etching Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to ... 03/23/06 - 20060063368 - Reduction of a feature dimension in a nano-scale device Nano-scale devices and methods provide reduced feature dimensions of features on the devices. A surface of a device substrate having a pattern of spaced apart first nanowires is consumed, such that a dimension of the first nanowires is reduced. A second nanowire is formed in a trench or gap between ... 03/23/06 - 20060063367 - Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a radio electronic device mounting the semiconductor device. ... 03/02/06 - 20060046462 - Circuitized substrate, method of making same and information handling system using same A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors. ... 02/23/06 - 20060040489 - Multi-layered structure forming method, method of manufacturing wiring substrate, and method of manufacturing electronic apparatus There is provided a multi-layered structure forming method comprising: (A) forming a first insulating material layer containing a first photo-curing material on a substrate; (B) semi-hardening the first insulating material layer by radiating light having a first wavelength to the first insulating material layer; (C) forming a conductive material layer ... 02/09/06 - 20060030142 - Semiconductor power device having a top-side drain using a sinker trench A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial ... 02/09/06 - 20060030141 - Method to form an interconnect Embodiments of methods, apparatuses, devices, and/or systems for forming an interconnect are described. ... 02/02/06 - 20060024945 - Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask Disclosed is a method for fabricating a semiconductor device by using an amorphous carbon layer as a sacrificial hard mask. The method includes the steps of: forming an amorphous carbon layer on an etch target layer; forming a photoresist pattern on the amorphous carbon layer; etching the amorphous carbon layer ... 01/26/06 - 20060019484 - Wafer-leveled chip packaging structure and method thereof This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first ... 01/26/06 - 20060019483 - Method for production of an integrated circuit arrangement, in particular with a capacitor arrangement, as well as an integrated circuit arrangement A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In ... 01/26/06 - 20060019482 - Air gap interconnect structure and method thereof Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of ... 01/19/06 - 20060014373 - Method for finishing metal line for semiconductor device A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface ... 01/19/06 - 20060014372 - Semiconductor device and method for fabricating the same The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; ... 01/12/06 - 20060009025 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, including the steps of: forming first and second insulation films on a substrate; sequentially forming an organic sacrificing layer and first and second mask layers thereon; forming a wiring groove pattern in the second mask layer; forming a connection hole pattern for forming ... 01/12/06 - 20060009024 - Method for forming a metal line in a semiconductor device Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it possible to shrink ... 01/05/06 - 20060003571 - Method for forming contact hole in semiconductor device Disclosed is a method for forming a plurality of contact holes in a semiconductor device. The method includes the steps of: forming an oxide-based layer on a substrate; forming an organic polymer layer on the oxide-based layer; forming a photoresist pattern on the organic polymer layer to form the plurality ... 01/05/06 - 20060003570 - Method and apparatus for electroless capping with vapor drying Embodiments of the invention relate to a method and apparatus for forming an electroless capping layer over the copper features of a substrate including one or more vapor drying steps. An embodiment of the method includes vapor drying the substrate; optionally applying a dielectric clean solution to the substrate; optionally ... 12/29/05 - 20050287788 - Manufacturing method of nanowire array This specification discloses a manufacturing method of nanowire array. The method includes the steps of: providing a substrate; forming an insulating layer on the substrate; forming a metal catalyst layer on the insulating layer by spin on glass (SOG), the metal catalyst being Au, Ag, or Pt; forming a covering ... 12/29/05 - 20050287787 - Porous ceramic materials as low-k films in semiconductor devices A method for selecting and forming a low-k, relatively high E porous ceramic film in a semiconductor device is described. A ceramic material is selected having a relatively high Young's modulus and relatively lower dielectric constant. The k is reduced by making the film porous. ... 12/29/05 - 20050287786 - Device and method using isotopically enriched silicon The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped ... 12/15/05 - 20050277283 - Chip structure and method for fabricating the same A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first ... 12/15/05 - 20050277282 - Method of manufacturing wiring substrate A method of manufacturing a wiring substrate of the present invention, includes a step of preparing a substrate containing a semi-cured resin layer or a thermo plastic resin layer, a step of forming a through hole that passes through the substrate, a step of inserting a conductive parts in the ... 12/15/05 - 20050277281 - Compliant interconnect and method of formation A method for making a compliant interconnect with two or more layers of metal is described herein. ... 12/08/05 - 20050272248 - Low-k dielectric structure and method A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying permeable material. As a result, at least one void is created, contributing to ... 12/08/05 - 20050272247 - Substrate processing method and fabrication process of a semiconductor device A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so ... 12/08/05 - 20050272246 - Integrated capacitor for rf applications A precision RF passive component comprising: a silicon substrate; a first dielectric layer deposited above the silicon substrate; a first metal layer formed above the first dielectric layer; a second dielectric layer formed above the first metal layer; and a second metal layer formed above the second dielectric layer. In ... 12/08/05 - 20050272245 - Method for forming contact plug of semiconductor device Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing ... 12/01/05 - 20050266673 - Reduced electromigration and stressed induced migration of copper wires by surface coating The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by ... 11/17/05 - 20050255686 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device having a build-up layer for wiring between semiconductor elements and external connection terminals is disclosed. The method comprises steps of forming a rewiring layer on a wafer, placing the wafer on a stretchable dicing tape, dicing the wafer placed on the dicing tape, ... 11/10/05 - 20050250309 - Semiconductor device using low-k material as interlayer insulating film and its manufacture method A semiconductor element is formed over a surface of a semiconductor substrate. A first insulating film is formed over the surface of the semiconductor substrate, the first insulating film covering the semiconductor element. A second insulating film is formed over the first insulating film, the second insulating film having a ... 11/10/05 - 20050250308 - Method for manufacturing semiconductor device The present invention provides a method for manufacturing a semiconductor device having high characteristic and reliability. The etching damage during dry etching after forming an electrode or a wiring over an insulating film is prevented. The damage is suppressed by forming a conductive layer so that charged particles due to ... 11/10/05 - 20050250307 - Interconnection structures for semicondcutor devices and methods of forming the same An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. ... 11/03/05 - 20050245066 - Methods of forming solder bumps on exposed metal pads and related structures A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In ... 11/03/05 - 20050245065 - Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same of the present invention realize an excellent manufacturing stability. The semiconductor device comprises a semiconductor substrate, a metal interconnect, which is formed over the semiconductor substrate, composed of copper containing metals, and a connection plug, which is composed of copper ... 11/03/05 - 20050245064 - Method for preventing voids in metal interconnects A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, ... 11/03/05 - 20050245063 - Method for forming suspended transmission line structures in back end of line processing A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the ... 10/27/05 - 20050239279 - Integrated circuits including spacers that extend beneath a conductive line and methods of fabricating the same Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sidewalls therebetween. An insulating spacer is formed to extend along ... 10/27/05 - 20050239278 - Process of forming a composite diffusion barrier in copper/organic low-k damascene technology A method of forming a composite barrier layer comprising the following steps. A substrate having a dielectric layer formed thereover is provided. An opening exposing a first portion of the substrate is formed within the dielectric layer. A dielectric flash layer is formed within the opening and over the first ... 10/20/05 - 20050233574 - Capacitance reduction by tunnel formation for use with a semiconductor device A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first ... 10/20/05 - 20050233573 - Method for fabricating semiconductor device A method for fabricating a semiconductor device for reducing coupling noise resulting from high integration of devices, comprises the steps of forming a plurality of metal wiring leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate having a predetermined under layer; forming an insulating ... 10/20/05 - 20050233572 - Dual damascene structure formed of low-k dielectric materials A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material ... 10/13/05 - 20050227476 - Method for fabricating a semiconductor device A semiconductor device has a multi-layer interconnection structure with a first interlayer insulation film and a second interlayer insulation film that is formed on the first interlayer insulation film and has a hardness and an elastic modulus larger than those of the first interlayer insulation film, and is fabricated by ... 09/01/05 - 20050191840 - Method of forming a dual damascene structure An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently ... 08/25/05 - 20050186774 - Method of using micro-contact imprinted features for formation of electrical interconnects for substrates An imprinting stamp to imprint an opening in a material layer in which the imprint stamp has a coating of a seed material. The seed material is transferred onto the surface within the opening to operate as a seed for filling the opening. In one embodiment, low surface energy material ... 08/25/05 - 20050186773 - Methods and structures for metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” ... 08/11/05 - 20050176236 - Method of forming interconnection lines for semiconductor device The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern ... 08/04/05 - 20050170631 - Manufacturing method for wiring substrates A manufacturing method for wiring substrates for photographing a positioning mark formed with a high precision using reflected light and executing a relative positioning operation between a wiring substrate workpiece and an exposure mask based thereon. The method steps include successively laminating a conductor layer and dielectric layer on a ... 07/28/05 - 20050164487 - Formation of a tantalum-nitride layer A method of forming a tantalum nitride layer for integrated circuit fabrication is disclosed. In one embodiment, the method includes forming a tantalum nitride layer by chemisorbing a tantalum precursor and a nitrogen precursor on a substrate disposed in a process chamber. A nitrogen concentration of the tantalum nitride layer ... 07/14/05 - 20050153534 - Electric contacts and method of manufacturing thereof, and vacuum interrupter and vacuum circuit breaker using thereof An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road side transformer using thereof. The contact member is composed of a ... 07/14/05 - 20050153533 - Semiconductor manufacturing method and semiconductor manufacturing apparatus Ammonium gas is supplied by means of a gas supply apparatus to a reaction tube containing a semiconductor wafer manufactured with etching and ashing cleaning processing in a predetermined semiconductor manufacturing process, further the reaction tube is heated by a heater, and thus the semiconductor water is made to undergo ... 06/30/05 - 20050142838 - Method of fabricating a test pattern for junction leakage current A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the ... 06/16/05 - 20050130403 - Stacked local interconnect structure and method of fabricating same A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically ... 06/16/05 - 20050130402 - Semiconductor local interconnect and contact An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed ... 06/16/05 - 20050130401 - Methods of forming metal interconnection lines in semiconductor devices A method of forming metal interconnection line for a semiconductor device being capable of forming a plug without voids irrespective of aspect ratios is provided. In one example, the method includes forming a first metal layer on a semiconductor substrate; forming a second metal layer on the first metal layer; ... 06/09/05 - 20050124149 - Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A ... 06/09/05 - 20050124148 - Method for embedding a component in a base and forming a contact This publication discloses a method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base. Thus, the base structure is more or less manufactured around the semiconductor ... 06/02/05 - 20050118798 - Gate-contact structure and method for forming the same A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation ... 06/02/05 - 20050118797 - Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in the first insulation layer to expose a portion of ... 06/02/05 - 20050118796 - Process for forming an electrically conductive interconnect An electrically conductive metallic interconnect in a trench or via in a dielectric is provided by depositing a first liner layer on the walls and bottom of the trench or via; removing residual contamination from the bottom of the trench or via; depositing a second liner layer in the trench; ... ### FreshPatents.com Support - Terms & Conditions |