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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material > Forming Solder Contact Or Bonding Pad Forming Solder Contact Or Bonding PadForming Solder Contact Or Bonding Pad patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087545 - Method of manufacturing image display device The present application relates to a method of manufacturing an image display device. The manufacturing method includes a step of arranging a side wall made of metal extending along an inner peripheral edge of a front substrate or a back substrate on the inner peripheral edge in a state that ... 04/19/07 - 20070087544 - Method for forming improved bump structure Methods for forming an improved bump structure on a semiconductor device are provided. In one embodiment, a substrate is provided having at least one contact pad formed thereon. A first passivation layer is formed over the substrate, the first passivation layer having at least one opening therein exposing a portion ... 04/12/07 - 20070082475 - Method for forming bonding pad and semiconductor device having the bonding pad formed thereby A first insulating film is formed on a substrate or a lower metal wiring, and a first metal layer is formed on the first insulating film. A second insulating film and a third insulating film are formed on the first insulating film and the first metal layer, and the third ... 03/22/07 - 20070066044 - Semiconductor manufacturing method In a stealth dicing process for a semiconductor device with a low dielectric constant layer, the occurrence of poor appearance such as a defective shape or discoloration in the layer is reduced or prevented as follows. A low dielectric constant layer is formed in an interlayer insulating layer formed on ... 03/15/07 - 20070059916 - Manufacturing method of semiconductor device A lead for external connection is formed of the alloy (42Alloy) of Fe and Ni, and a plating film which includes alloy of Sn and Cu is formed on the surface. Next, using a heat-treat furnace, the heat treatment at the temperature beyond melting-point T0 of the plating film is ... 03/08/07 - 20070054483 - Integrated die bumping process An integrated die bumping process includes providing a load board, defining a plurality of die regions on a surface of the load board for placing dice of a plurality of die specifications, affixing a plurality of dice respectively on the die regions according to the plurality of die specifications, and ... 03/01/07 - 20070048999 - Method for fabricating semiconductor component having conductors and bonding pads with wire bondable surfaces and selected thickness A method for fabricating a semiconductor component includes the step of providing a semiconductor die having a die contact and at least one integrated circuit in electrical communication with the die contact. The method also includes the steps of forming a first polymer layer on the die, forming a conductor ... 03/01/07 - 20070048998 - Method for fabricating semiconductor components encapsulated, bonded, interconnect contacts on redistribution contacts A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The ... 03/01/07 - 20070048997 - Chip package structure and method for manufacturing bumps A method for manufacturing bumps is provided. First, a first metal layer is formed on a substrate. Then, a patterned second metal layer is formed on the first metal layer. Then, flat bumps are formed on the second metal layer. Finally, the first metal layer is patterned to form bond ... 03/01/07 - 20070048996 - Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that ... 02/22/07 - 20070042592 - Novel approach to high temperature wafer processing At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows ... 02/22/07 - 20070042591 - Signal routing on redistribution layer A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other. The passivation layer is formed ... 02/15/07 - 20070037376 - Method and apparatus for fine pitch solder joint According to one embodiment of the invention, a method of assembling a package has been provided that includes coupling a plurality of solder balls to a first surface of a substrate. At least one of the plurality of solder balls is in communication with a trace that extends from the ... 02/08/07 - 20070032064 - Use of an internal on-chip inductor for electrostatic discharge protection of circuits which use bond wire inductance as their load A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an ... 02/01/07 - 20070026660 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device, including: (a) forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; (b) fusing the resin layer without being cured and shrunk by a first energy supply processing; (c) forming a resin boss by curing ... 02/01/07 - 20070026659 - Post last wiring level inductor using patterned plate process A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level. ... 01/25/07 - 20070020911 - Self alignment features for an electronic assembly Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The ... 01/25/07 - 20070020910 - Photoresist stripper composition and methods for forming wire structures and for fabricating thin film transistor substrate using composition A photoresist stripper composition, a method for forming wire structures thereby, and a method of fabricating a thin film transistor substrate using the composition. The photoresist stripper composition includes about 50 WT % to about 70 WT % of butyldiglycol, about 20 to about 40 WT % of an alkylpyrrolidone, ... 01/25/07 - 20070020909 - Forming of conductive bumps for an integrated circuit A method for forming conductive bumps on conductive pads formed on an electronic circuit wafer, comprising the steps of: including forming a resist mask with holes above the pads; depositing balls in the holes; performing a thermal processing to melt the balls; and eliminating the mask. ... 01/25/07 - 20070020908 - Multilayer structure having a warpage-compensating layer A multilayer structure is provided that includes a semiconductor member having opposing first and second major surfaces, a warpage-compensating layer deposited on the first major surface, and a substrate bonded to the second major surface. The warpage-compensating layer has a stiffness and a coefficient of thermal expansion keyed to the ... 01/18/07 - 20070015351 - Process or making a semiconductor device having a roughened surface An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a ... 01/11/07 - 20070010083 - Method of realizing direct bonding between metal wires and copper pads by means of thermosonic wire bonding using shielding gas spraying device Discloses is a method of realizing direct bonding between metal wires and copper pads by means of thermosonic wire bonding using a shielding gas spraying device, where a shielding gas is provided between metal wires and a chip with copper pads during thermosonic wire bonding to form a gas shielding ... 12/21/06 - 20060286790 - Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device includes preparing a semiconductor substrate having an electrode pad, a passivation film having an opening overlapping the electrode pad and an oxidized film formed in the opening, forming a resin projection on the passivation film, forming a metal layer on the passivation film ... 12/14/06 - 20060281294 - Method of forming a penetration electrode and substrate having a penetration electrode A method of forming a penetration electrode in which an electroconductive substance is inserted into a micropore that has one end blocked off only by wiring and a pad formed by an electroconductive substance without the wiring and pad being broken. In this method of forming a penetration electrode, an ... 12/14/06 - 20060281293 - Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the ... 12/07/06 - 20060276023 - Method for forming bumps A method for forming bumps is disclosed. First, a substrate having an under bump metallurgy (UBM) layer thereon is provided. Next, a patterned photoresist is disposed over the surface of the UBM layer, in which an opening is formed within the photoresist to expose part of the UBM layer. Next, ... 12/07/06 - 20060276022 - Capping copper bumps A structure including a substrate, a copper bump formed over the substrate, and a barrier layer comprising an alloy of at least one of iron and nickel, formed over the copper bump, and methods to make such a structure. ... 11/23/06 - 20060264021 - Offset solder bump method and apparatus An apparatus, method, and system for integrated circuit packaging having an offset solder bump are disclosed herein. A semiconductor substrate has a bond pad and a passivation layer located on an active surface thereof. A solder terminal contacts both the bond pad and passivation layer. A solder bump contacts the ... 11/16/06 - 20060258139 - Manufacturing method for wiring circuit substrate A method of making a microelectronic element includes making a connection component by providing a metal layer having a top surface and a bottom surface, providing a dielectric layer over the top surface of the metal layer and forming openings in the dielectric layer to expose portions of the top ... 11/16/06 - 20060258138 - Methods for fabricating fluid injection devices Methods for fabricating fluid injection devices. A patterned sacrificial layer is formed on a substrate. A patterned first structural layer is formed on the substrate covering the sacrificial layer. At least one fluid actuator is formed on the structural layer. A first passivation layer is formed on the first structural ... 11/16/06 - 20060258137 - Semiconductor device and fabrication method thereof A semiconductor device and a fabrication method thereof ate provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the ... 11/16/06 - 20060258136 - Method of forming a metal trace Disclosed is a method of forming a metal trace on a substrate. The method includes inkjet printing a chemical ink comprising a metal containing compound on the substrate surface to form an ink drop thereon, and heating the substrate to a suitable elevated temperature. The ink drop undergoes at least ... 11/16/06 - 20060258135 - Semiconductor integrated circuit Each of plural semiconductor integrated circuits existing on a semiconductor wafer is provided with a function circuit (3), plural pads (4), and wirings (8) which are electrically connected to the pads (4) and contact bumps of a probe card (7), wherein at least two wirings (8a) and (8b) simultaneously contact ... 11/09/06 - 20060252247 - Processing apparatus for electroplating conductive bumps on organic circuit board A processing apparatus for electroplating conductive bumps on an organic circuit board includes a surface cleaning unit for removing organic contaminant on the surface of conductive layer on the circuit board, a rinsing unit for rinsing the surface of conductive layer, a surface activating unit for removing a metal oxide ... 11/09/06 - 20060252246 - Image sensor module and method thereof The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a ... 11/09/06 - 20060252245 - Fabrication method of under bump metallurgy structure A fabrication method of under bump metallurgy (UBM) structure is provided. A blocking layer is applied over a surface of a semiconductor element formed with at least one bond pad and a passivation layer thereon. The passivation layer covers the semiconductor element and exposes the bond pad, and the blocking ... 11/02/06 - 20060246705 - Methods of forming wire bonds for semiconductor constructions The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with ... 11/02/06 - 20060246704 - Multi-chip module and method of manufacture A multi-chip module and a method for manufacturing the multi-chip module. A first semiconductor chip is mounted to a support substrate and a second semiconductor chip is mounted to the first semiconductor chip. The second semiconductor chip has a smaller dimension than the first semiconductor chip. A spacer is coupled ... 11/02/06 - 20060246703 - Post bump passivation for soft error protection A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top ... 10/05/06 - 20060223298 - Integrated circuit and methods of redistributing bondpad locations Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an integrated circuit includes providing an integrated circuit comprising an inner lead bondpad. A first insulative passivation layer is formed over the integrated circuit. A bondpad-redistribution line is formed ... 09/28/06 - 20060216919 - Method for manufacturing semiconductor device, and method and structure for implementing semiconductor device A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the ... 08/24/06 - 20060189117 - Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the ... 08/24/06 - 20060189116 - Dual metal stud bumping for flip chip applications A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive ... 08/03/06 - 20060172523 - Method for delineating a conducting element which is disposed on an insulating layer, and device and transistor thus obtained A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas of the conducting layer are ... 07/20/06 - 20060160347 - Method of manufacturing semiconductor device and method of treating electrical connection section A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section. ... 07/20/06 - 20060160346 - Substrate bump formation A layer of metal may be formed under a layer of solder in forming solder bumps. The metal may reduce the amount of solder necessary and may result in a corresponding reduction in solder defects. ... 07/06/06 - 20060148231 - Integrated die bumping process An integrated die bumping process includes providing a load board, defining a plurality of die regions on a surface of the load board for placing dice of a plurality of die specifications, affixing a plurality of dice respectively on the die regions according to the plurality of die specifications, and ... 06/29/06 - 20060141760 - Method for producing an electrical component To expose a submerged bondable terminal pad in a component that includes at least two substrates which are joined with each other, it is proposed that grooves of relatively shallow depth be provided on the connecting surface of the second substrate before the two substrates are joined. After the two ... 06/22/06 - 20060134901 - Hot-melt underfill composition and methos of application This invention provides a process for applying a wafer level underfill comprising: providing a solvent-free hot-melt underfill composition; melting the underfill; applying the underfill in a uniform layer to the active side of a semiconductor wafer; returning the underfill to a solid state; optionally B-staging the underfill; optionally removing any ... 06/15/06 - 20060128134 - Method for re-routing lithography-free microelectronic devices A method for producing a chip-scale electronic package produced at a substrate level, the substrate including at least one chip having input/output pads on a substrate face. The method a) forms, using a complex mold or stencil, an insulating stress relaxation layer on the front face, the relaxation layer covering ... 06/08/06 - 20060121718 - Manufacturing method of chip integrated substrate A manufacturing method of a chip integrated substrate is disclosed. The manufacturing method includes a first step that forms a wiring structure to be connected to a semiconductor chip on a first core substrate; a second step that disposes the semiconductor chip on a second core substrate; and a third ... 06/08/06 - 20060121717 - Bonding structure and fabrication thereof Bonding structure and method of fabricating the same. The bonding structure of the invention includes an insulating layer having at least one metal segment formed thereon and a bonding pad over the metal segment, wherein the bonding pad is substantially surrounded by a first passivation layer comprising a first atomic ... 06/01/06 - 20060115974 - Method of making a circuitized substrate A circuitized substrate and a method of making the circuitized substrate are provided. The circuitized substrate includes a substrate having a conductive pad thereon. A first layer of solder enhancing material is positioned on the conductive pad, the first layer of solder enhancing material includes a first region and a ... 05/25/06 - 20060110907 - Method for removing resin mask layer and method for manufacturing solder bumped substrate Using a dry film resist that is a photosensitive resin, a resin mask layer is formed around electrodes on a substrate. A solder precipitating composition is applied on the substrate, and this solder precipitating composition is heated to precipitate solder on the surface of the electrodes. Subsequently, in removing the ... 05/25/06 - 20060110906 - Wafer alignment method The present invention relates to a wafer alignment method. The wafer alignment method includes the steps of forming first bonding pads and first wafer alignment marks of a convex shape on predetermined regions of a first semiconductor substrate in which a first device is formed, forming second bonding pads on ... 05/25/06 - 20060110905 - High surface area aluminum bond pad for through-wafer connections to an electronic package A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads. ... 05/11/06 - 20060099791 - Bonded wafer and method of producing bonded wafer The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present ... 05/11/06 - 20060099790 - Method of implanting at least one solder bump on a printed circuit board A method of implanting at least one solder bump on a surface of a printed circuit board (PCB) on which at least one soldering pad is exposed since the solder bump intended to be formed thereon is missing is described. The method comprises the steps of: first, forming at least ... 05/11/06 - 20060099789 - Micro lead frame packages and methods of manufacturing the same Microelectronic packages include a microelectronic element and portions of a lead frame disposed beneath the microelectronic element. The lead frame may be laminated with a dielectric element and the resulting laminate may be punched to remove the bus bar included in the lead frame, thereby forming an in-process unit having ... 05/04/06 - 20060094224 - Bumping process and structure thereof A bumping process is provided. The bumping process comprises the steps of: firstly, providing a wafer; next forming an under bump metallurgy (UBM) on the active surface of the wafer; then, forming a photo-resist layer on the active surface of the wafer and forming at least an opening in the ... 05/04/06 - 20060094223 - Fabrication method of a wafer structure A wafer fabricating method at least includes the steps of providing a wafer having an active surface with a plurality of pads, forming a plurality of bumps on the pad, and forming an organic protective layer on the bump and the active surface. Besides improving the quality of the wafer, ... 03/30/06 - 20060068580 - Semiconductor device and fabrication method thereof The semiconductor device of the present invention and the method of the present invention, for forming the semiconductor device, form: a penetrating hole in a semiconductor wafer which has a first insulating film and an electrode pad formed on a first face of the semiconductor wafer, the penetrating hole being ... 03/30/06 - 20060068579 - Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to ... 03/23/06 - 20060063365 - Aluminum cap for reducing scratch and wire-bond bridging of bond pads A method of manufacturing a semiconductor device and structure thereof. The method includes providing a workpiece, the workpiece having at least one conductive pad partially exposed through an opening in a passivation layer, the passivation layer having a top surface and the opening in the passivation layer having sidewalls. A ... 03/16/06 - 20060057834 - Semiconductor device and fabrication process thereof A semiconductor device includes a conductive layer with a plurality of wires, and a bonding pad formed in a region overlapping with the plurality of wires of the conductive layer. One of the wires is connected to the bonding pad, and an insulating protective film is formed between the remaining ... 03/16/06 - 20060057833 - Method of forming solder ball, and fabricating method and structure of semiconductor package using the same A method of forming solder balls may involve forming bumps through wire boding on land patterns of a circuit substrate. Solder cream may be applied to the bumps through screen printing. The solder cream may be melted via reflow to form solder balls in which the bumps are embedded. ... 03/16/06 - 20060057832 - Wafer level packages and methods of fabrication A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least ... 03/16/06 - 20060057831 - Wire bond pads A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on ... 03/09/06 - 20060051951 - Method of clearing electrical contact pads in thin film sealed oled devices A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad. ... 03/02/06 - 20060046461 - Method for creating electrically conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material ... 02/09/06 - 20060030139 - Methods of forming lead free solder bumps and related structures Methods of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate. A nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and ... 02/02/06 - 20060024944 - Metal pad of semiconductor device and method for bonding the metal pad A method of bonding a metal pad of the semiconductor device including a step of forming a metal pad in a pad forming area of a chip and another pad forming area of another chip. The another chip is adjacent to the chip, and both the chip and the another ... 02/02/06 - 20060024943 - Prevention and control of intermetallic alloy inclusions that form during reflow of pb free, sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless ni(p) metallization is present In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of ... 02/02/06 - 20060024942 - Semiconductor constructions comprising multi-level patterns of radiation-imageable material; and methods of forming wire bonds for semiconductor constructions The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with ... 01/26/06 - 20060019480 - Method for fabricating pad redistribution layer A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over ... 01/19/06 - 20060014369 - Stud electrode and process for making same A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell ... 12/08/05 - 20050272241 - Method for forming interconnects on thin wafers A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing ... 12/08/05 - 20050272240 - Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact ... 12/01/05 - 20050266669 - Method and apparatus to eliminate galvanic corrosion on copper doped aluminum bond pads on integrated circuits The present invention is an electronic interconnect comprising a bond pad consisting essentially of aluminum and copper and configured for use in semiconductor electronic devices to couple a bond wire to an integrated circuit package. The bond pad has an oxide coating residing on at least a topmost surface of ... 12/01/05 - 20050266668 - Semiconductor device and method of manufacturing the same A semiconductor device comprises a semiconductor element having first electrode pads and solder bumps, and a substrate having second electrode pads connected to the first electrode pads via the solder bumps. The semiconductor element has an insulating film with a low dielectric constant. The group of the solder bumps is ... 12/01/05 - 20050266667 - Structure and method of forming metal buffering layer A structure and method of forming a metal buffering layer during the formation of a redistribution layer is provided. It only changes a mask to form the metal buffering layer and circuit traces simultaneously. The metal buffering layer can increase the flatness of the dielectric layer covering on the metal ... 11/24/05 - 20050260844 - Package with barrier wall and method for manufacturing the same A ball grid array (BGA) package that may suppress flash contamination may include a flash contamination barrier wall. The barrier wall may be a portion of a copper pattern provided on a substrate. During a molding process, the flash contamination barrier may prevent a flash from contaminating a ball land. ... 11/10/05 - 20050250303 - Method for bonding ic chips to substrates incorporating dummy bumps and non-conductive adhesive An IC chip/substrate assembly bonded together by a non-conductive adhesive and a method for forming the assembly. The assembly consists of an IC chip that has bumps formed on an active surface, a substrate that has bond pads formed on a top surface, wherein at least one of the IC ... 11/03/05 - 20050245060 - Package design using thermal linkage from die to printed circuit board A substrate is provided that may include an area designated for mounting of an integrated circuit and one or more areas for retaining a thermal interface material proximate the integrated circuit mounting area. A thermal interface material containment area(s) may be formed by creating a through-hole in the substrate, or ... 11/03/05 - 20050245059 - Method for making an interconnect pad An interconnect pad is made to have a convex shape which is a shape that has been found to useful in improving the reliability of solder joints. A seed pillar is formed by plating over a metal layer. This seed pillar is smaller than the intended size of the interconnect ... 10/27/05 - 20050239276 - Bump forming method and system using bump material including liquid A bump forming method for forming bumps on pads of a test piece which is a semiconductor wafer or chip includes a fastening process of pouring a bump material including liquid toward a target face of a mask substrate in which a plurality of holding holes are provided, and making ... 10/20/05 - 20050233568 - Method for manufacturing semiconductor device having solder layer A method for manufacturing a semiconductor device having a solder layer includes the steps of: grinding a mounting surface of a semiconductor chip; etching the mounting surface of the chip; forming an electrode on the mounting surface of the chip; assembling the chip, the solder layer and a base in ... 10/20/05 - 20050233567 - Method of manufacturing multi-stack package A method of manufacturing a multi-stack package that ensures easy application of a solder paste or a flux. The method includes forming a first package comprising a first substrate on which bumps are arranged and a second package comprising a second substrate on which electrode pads corresponding to the bumps ... 10/13/05 - 20050227474 - Method of connecting base materials The present invention is aimed at providing a method of connecting base materials capable of forming metal terminals having a uniform height and smooth surface with a low cost, and of realizing a low-damage mounting, in which a work is planarized while keeping the temperature of the insulating film, possibly ... 10/06/05 - 20050221597 - Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor A mounting substrate includes an imprinted structure on one side for containing electrical bumps. The imprinted structure is imprinted and also cured under conditions that allow retention of significant features of the cured polymer film. A chip package is also made of the imprinted structure. A computing system is also ... 09/29/05 - 20050215043 - Low fabrication cost, high performance, high reliability chip scale package The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is ... 09/22/05 - 20050208747 - Method of routing an electrical connection on a semiconductor device and structure therefor In one embodiment, conductors of a semiconductor device are routed to a contact platform of the semiconductor device by using electroless plating and screen-printing techniques. ... 09/01/05 - 20050191836 - Method to prevent passivation layer peeling in a solder bump formation process A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous ... 08/25/05 - 20050186769 - Hexagonal array structure for ball grid array packages Solder balls may be arranged in hexagonal array on an integrated circuit package. The hexagonal array may increase the solder ball density, reducing solder ball fatigue. In some embodiments, the hexagonal array may be utilized under the die shadow and an orthogonal array may be used outbound thereof. ... 08/11/05 - 20050176232 - Methods and apparatus for integrated circuit ball bonding with substantially perpendicular wire bond profiles Techniques for ball bonding wires in an integrated circuit are provided which allow formation of desired wire bond profile shapes for optimal performance. A wire is ball bonded to a first bond site in the integrated circuit with a bonding tool and at least one bend is formed in the ... 08/11/05 - 20050176231 - Bumping process of light emitting diode A bumping process for a light emitting diode (LED) chip is provided. Firstly, a LED chip with a plurality of electrodes is provided, then a pattern plate having a plurality of openings is disposed on the LED chip, and the electrodes are correspondingly exposed by the openings. Then, a plurality ... 08/04/05 - 20050170629 - Method of fabricating a low cost zener diode chip for use in shunt-wired miniature light strings A process for fabricating Zener diodes that does not require the use of photomasks. An oxide layer is grown on a silicon substrate which is doped with an N-type dopant. The substrate is subsequently implanted with a P-type dopant, forming a PN junction. The substrate is then metallized for connecting ... 08/04/05 - 20050170628 - Forming a contact in a thin-film device An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the ... 08/04/05 - 20050170627 - Interconnect apparatus, system, and method An apparatus, system, and method for forming a connector including a frame, a conductor, and a solder ball formed on a conductive land of the conductor. The method includes depositing solder mask on a conductive pad of a conductor, depositing solder paste in the area defined by the solder mask, ... 07/28/05 - 20050164484 - Method of fabricating a pad over active circuit i.c. with meshed support structure An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, ... 07/28/05 - 20050164483 - Method of forming solder bump with reduced surface defects A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a ... 07/21/05 - 20050158978 - Hermetic passivation structure with low capacitance A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad ... 06/30/05 - 20050142835 - Method of disposing conductive bumps onto a semiconductor device and semiconductor devices so formed A method of forming conductive structures on the contact pads of a substrate, such as a semiconductor die or a printed circuit board. A solder mask is secured to an active surface of the substrate. Apertures through the solder mask are aligned with contact pads on the substrate. The apertures ... 06/23/05 - 20050136641 - Solder structures for out of plane connections and related methods Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the ... 06/23/05 - 20050136640 - Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same A thinned die is disposed on a heat sink and bonded by a thermal interface material (TIM) that includes a gold-tin solder. The thinned die exhibits a die-effective coefficient of thermal expansion (CTE) that substantially matches the CTE of the heat sink. A process of bonding the die includes thermal ... 06/23/05 - 20050136639 - Pin-deposition of conductive inks for microelectrodes and contact via filling A system for metalization of an integrated microsystem. The system comprises providing a substrate and applying a conductive material to the substrate by taking up small aliquots of conductive material and releasing the conductive material onto the substrate to produce a circuit component. ... ### FreshPatents.com Support |