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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > To Form Ohmic Contact To Semiconductive Material To Form Ohmic Contact To Semiconductive MaterialTo Form Ohmic Contact To Semiconductive Material patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082474 - Process for making a metal seed layer An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition. ... 04/12/07 - 20070082473 - Process for low resistance metal cap An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition. ... 04/12/07 - 20070082472 - Method of manufacturing contact hole A method of manufacturing contact hole is provided. First, a mask layer is formed on a substrate and a plurality of trenches is formed in the mask layer along two directions that cross over each other. The depth of the trenches is not greater than the thickness of the mask ... 03/22/07 - 20070066042 - Method of forming an electrical contact In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed ... 03/15/07 - 20070059915 - Method of forming an electrical contact In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed ... 03/15/07 - 20070059914 - Method of forming micro patterns in semiconductor devices A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface ... 03/15/07 - 20070059913 - Capping layer to reduce amine poisoning of photoresist layers An apparatus for reducing amine poisoning of photoresist layers comprises a substrate, an etch stop layer containing amines formed over the substrate, and a dense capping layer formed directly on the etch stop layer, wherein the dense capping layer substantially prevents the amines from diffusing out of the etch stop ... 03/08/07 - 20070054482 - Semiconductor device fabrication method According to one aspect of the invention, there is provided a semiconductor device fabrication method having: forming a film on a semiconductor substrate; forming a mask comprising a predetermined pattern on the film; etching one of the film and the semiconductor substrate by using the mask; and performing at least ... 03/01/07 - 20070048995 - Method for production of semiconductor devices A method for production of semiconductor devices which includes the steps of forming, on an interlayer insulating film formed on a substrate, a copper-containing conductive layer in such a way that its surface is exposed, performing heat treatment with a reducing gas composed mainly of hydrogen on the surface of ... 03/01/07 - 20070048994 - Methods for forming through-wafer interconnects and structures resulting therefrom The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the ... 03/01/07 - 20070048993 - Semiconductor product and method for forming a semiconductor product A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling ... 03/01/07 - 20070048992 - Integrated pvd system using designated pvd chambers A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one load lock chamber, at least one first ... 03/01/07 - 20070048991 - Copper interconnect structures and fabrication method thereof Copper interconnect structures for interconnection. The interconnect structure has a copper recess in a damascene structure with copper filled in a via/trench of a dielectric layer. Furthermore, the interconnect structure can also have a metal cap filled the copper recess. ... 02/22/07 - 20070042590 - Method for maufacturing semiconductor device A diffusion barrier film which covers the surface of a first insulating film provided on an upper surface of a semiconductor substrate, a second insulating film which covers over the diffusion barrier film, and a cap film which covers the second insulating film, are sequentially laminated. A wiring trench portion, ... 02/22/07 - 20070042589 - Composite inter-level dielectric structure for an integrated circuit A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on ... 02/22/07 - 20070042588 - Single damascene with disposable stencil and method therefore In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited ... 02/22/07 - 20070042587 - Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on the substrate while under a vacuum of the type found in a vacuum chamber. A catalytic layer is ... 02/15/07 - 20070037375 - Semiconductor memory devices having contact pads with silicide caps thereon An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad ... 02/15/07 - 20070037374 - Semiconductor device and its manufacturing method A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of ... 02/08/07 - 20070032062 - Methods of forming dual-damascene metal wiring patterns for integrated circuit devices and wiring patterns formed thereby Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop ... 02/08/07 - 20070032061 - Methods of forming through-wafer interconnects and structures resulting therefrom Methods for forming conductive vias or through-wafer interconnects in semiconductor substrates and resulting through wafer interconnect structures are disclosed. In one embodiment of the present invention, a method of forming a through wafer interconnect structure includes the acts of forming an aperture in a first surface of a substrate, depositing ... 02/08/07 - 20070032060 - Method for forming conductive wiring and interconnects A method for forming conductive wiring is provided. First, a material layer having at least a trench is provided. A conductive material layer is formed on the material layer to fill the trench and cover the top surface of the material layer. A patterned mask layer is formed on the ... 02/08/07 - 20070032059 - Method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure This invention provides a method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor wafer (1) having a bulk region (1a) and an active region (1b); forming a plurality of contact trenches (5a-5f) in said semiconductor ... 02/08/07 - 20070032058 - Method of fabricating interconnect A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over the first dielectric layer and the metal layer. A surface treatment process is performed to the material ... 02/01/07 - 20070026657 - Methods of forming semiconductor devices with contact holes self-aligned in two directions and devices so formed A method of forming a semiconductor device can include forming a plurality of gate structure patterns including gates and first mask patterns stacked on a semiconductor substrate, the gate structure patterns being spaced apart from each other and extending in a first direction, forming a first interlayer insulating layer covering ... 02/01/07 - 20070026656 - Method and structure for landing polysilicon contact A method for fabricating an integrated circuit device, e.g., DRAM. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of MOS transistor devices overlying the semiconductor substrate. Each of the MOS transistor devices has a nitride cap and nitride sidewall spacers. Each of ... 01/25/07 - 20070020907 - Method of forming a connecting conductor and wirings of a semiconductor chip A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist ... 01/25/07 - 20070020906 - Method for forming high reliability bump structure Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the ... 01/25/07 - 20070020905 - Low resistance contact in a semiconductor device In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface ... 01/25/07 - 20070020904 - Selectively filling microelectronic features Some embodiments of the present invention include filling features using selective fill techniques. ... 01/04/07 - 20070004189 - Manufacturing method of semiconductor device The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming ... 12/28/06 - 20060292848 - Method for manufacturing nano-gap electrode device Provided is a method for manufacturing a nano-gap electrode device comprising the steps of: forming a first electrode on a substrate; forming a spacer on a sidewall of the first electrode; forming a second electrode on an exposed substrate at a side of the spacer; and forming a nano-gap between ... 12/28/06 - 20060292847 - Silver barrier layers to minimize whisker growth in tin electrodeposits The invention relates to a method of reducing tin whisker formation in a plated substrate that includes a surface layer comprising tin. The method includes providing on electroplatable portions of the substrate (a) an underlayer comprising silver or (b) a barrier layer that passes a mechanical load test when the ... 12/28/06 - 20060292846 - Material management in substrate processing Substrate processing systems and methods are described for processing substrates. The processing includes transferring electronic identification (ID) information of one or more materials contained in one or more processing subsystems. Materials are transferred between one or more material containers and respective one or more process cells during transfer events of ... 12/28/06 - 20060292845 - Processing substrates using site-isolated processing Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one ... 12/21/06 - 20060286788 - Method for making a wire nanostructure in a semiconductor film passage of a current between the first and the second terminals so as to form at least one continuous overthickness (R1, R2, R3) in the thin semiconductor film by migration of a fraction of the semiconductor material, under the action of the current, the continuous overthickness being formed along the ... 12/14/06 - 20060281291 - Method for manufacturing a metal-semiconductor contact in semiconductor components A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal-semiconductor or Schottky contact is produced only after the application of a protective layer system, ... 12/14/06 - 20060281290 - Semiconductor device and method of manufacturing the same In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel ... 12/07/06 - 20060276021 - Method for forming metal line of semiconductor device A method for forming a metal line of a semiconductor device includes: forming an insulating layer on a substrate; sequentially forming a first barrier metal layer and a metal layer on the insulating layer; forming a second barrier metal layer on the metal layer; coating a photoresist on the second ... 11/30/06 - 20060270207 - Reduced metal design rules for power devices A process for etching a thick aluminum contact layer of a semiconductor wafer comprises the formation of a wet etch photoresist mask and the opening of a window in the mask, followed by a wet etch of a first portion of the thickness of the contact layer exposed by the ... 11/30/06 - 20060270206 - Method of forming ohmic contact layer and method of fabricating light emitting device having ohmic contact layer A method of manufacturing an ohmic contact layer and a method of manufacturing a top emission type nitride-based light emitting device having the ohmic contact layer are provided. The method of manufacturing an ohmic contact layer includes: forming a first conductive material layer on a semiconductor layer; forming a mask ... 11/23/06 - 20060264020 - Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the ... 11/02/06 - 20060246699 - Process for electroless copper deposition on a ruthenium seed Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form ... 10/26/06 - 20060240656 - Method for forming contact of semiconductor device by using solid phase epitaxy process A method for forming a contact plug of a semiconductor device includes providing a plurality of junctions on a substrate; forming an inter-layer insulation layer over the substrate and the junctions; forming a plurality of contact holes to expose the junctions by etching the inter-layer insulation layer; forming contact layers ... 10/19/06 - 20060234487 - Method of forming semiconductor device having stacked transistors There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are ... 10/12/06 - 20060228877 - Patterned material layer, method of forming the same, microdevice, and method of manufacturing the same A method of forming a patterned material layer, the method comprising: a resist layer forming step of forming a resist layer on a substrate, the resist layer including a first photosensitive resin layer, an intermediate resin layer, and a second photosensitive resin layer; an exposing step; a developing step of ... 10/05/06 - 20060223297 - Method for fabricating semiconductor device First gate lines are formed on a substrate. An insulation layer is formed on the substrate and the first gate lines. The insulation layer disposed between the first gate lines is selectively etched, to thereby form first openings. Landing plugs are buried into the first openings. The insulation layer disposed ... 09/07/06 - 20060199363 - Microelectronic devices and methods for forming interconnects in microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled ... 09/07/06 - 20060199362 - Method of registering a spacer with a conducting track A method of producing a relief structure on a patterned conductor comprises the steps of; coating a layer of conductive material onto a transparent substrate, coating a layer of metal onto the layer of conductive material, coating a layer of photoresist onto the layer of metal, curing the layer of ... 09/07/06 - 20060199361 - Manufacturing method of one-time programmable read only memory An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with ... 09/07/06 - 20060199360 - Cladded silver and silver alloy metallization for improved adhesion and electromigration resistance In semiconductor integrated circuit and device fabrication interconnect metallization is accomplished by a clad Ag deposited on a SiO2 level on a Si surface. The clad Ag has a layer of an alloy of Ag and Al (5 atomic %) contacting the SiO2, a layer of substantially pure Ag and ... 08/24/06 - 20060189114 - Method of manufacturing semiconductor device and semiconductor device According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric ... 08/24/06 - 20060189113 - Metal nanoparticle compositions A metal nanoparticle composition for the fabrication of conductive features. The metal nanoparticle composition advantageously has a low viscosity permitting deposition of the composition by direct-write tools. The metal nanoparticle composition advantageously also has a low conversion temperature, permitting its deposition and conversion to an electrical feature on polymeric substrates. ... 08/24/06 - 20060189112 - Electronic devices fabricated by use of random connections Embodiments of the present invention are directed to methods for fabricating microscale-to-nanoscale interfaces. In numerous embodiments of the present invention, hybrid microscale/nanoscale crossbar multiplexers/demultiplexers provide for selection and control of individual nanowires through a set of microscale signal lines. In order to overcome the difficulty of aligning nanowires with submicroscale ... 08/24/06 - 20060189111 - Method of making cmos devices on strained silicon on glass A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; ... 08/17/06 - 20060183311 - Method for manufacturing semiconductor devices and plug A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first ... 08/17/06 - 20060183310 - Process for fabricating semiconductor device and method for generating mask pattern data A method of fabricating a semiconductor device including a first wiring pattern extending in a vertical direction and a second wiring pattern identical in geometry to the first wiring pattern and extending in a (horizontal) direction orthogonal to the vertical direction, including the steps of: employing linearly polarized illumination to ... 08/17/06 - 20060183309 - Method for manufacturing a patterned structure A method for forming a micro- or nano-pattern of a material on a substrate is presented. The method utilizes a buffer layer assisted laser patterning (BLALP). A layered structure is formed on the substrate, this layered structure being in the form of spaced-apart regions of the substrate defined by the ... 08/10/06 - 20060177999 - Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces Methods for forming interconnects in blind holes and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having microelectronic dies with integrated circuits and terminals electrically coupled to the integrated circuits. In one embodiment, the method ... 08/03/06 - 20060172522 - Method of fine patterning a metal layer A method of fine patterning a metal layer which includes depositing a metal layer on a substrate; depositing, on the metal layer, a mask layer having a different degree of electrolytic dissociation than that of the metal layer; making a patterned substrate body; and dipping the substrate body into an ... 08/03/06 - 20060172521 - Method for allocating resources in heterogeneous nanowire crossbars having defective nanowisre junctions Various embodiments of the present invention provide methods for allocating nanowire junctions in a nanowire crossbar having one or more randomly distributed non-functional crossbar nanowire junctions. In certain embodiments, the method constructs a circuit graph based on the circuit and constructs a crossbar graph based on the nanowire crossbar. A ... 07/20/06 - 20060160344 - Rhodium film and method of formation A method for the formation of rhodium films with good step coverage is disclosed. Rhodium films are formed by a low temperature atomic layer deposition technique using a first gas of rhodium group metal precursor followed by an oxygen exposure. The invention provides, therefore, a method for forming smooth and ... 07/13/06 - 20060154465 - Method for fabricating interconnection line in semiconductor device Provided is a method for fabricating an interconnection line in a semiconductor device. The method includes forming a dielectric layer pattern including a region for forming the interconnection line on a semiconductor substrate, forming a diffusion barrier layer on the dielectric layer pattern, forming a first adhesion layer on the ... 07/13/06 - 20060154464 - Semiconductor device and a method of fabricating a semiconductor device A semiconductor device includes a semiconductor substrate; a porous low k dielectric disposed on the semiconductor substrate having a plurality of trenches therein, the porous low k dielectric having an effective dielectric constant of 3.0 or less; a plurality of barrier layers provided on each surface of the trenches, each ... 06/29/06 - 20060141758 - Method of forming contact pads In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the ... 06/22/06 - 20060134900 - Method of forming a metal interconnection line in a semiconductor device using an fsg layer A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of the lower metal layer, forming ... 05/25/06 - 20060110903 - Method for formation of a contact in a semiconductor wafer In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing ... 05/25/06 - 20060110902 - Method and system for metal barrier and seed integration A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier ... 05/25/06 - 20060110901 - Minimizing resist poisoning in the manufacture of semiconductor devices The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via ... 05/18/06 - 20060105558 - Inter-metal dielectric scheme for semiconductors System and method for providing an inter-metal dielectric that prevents or reduces film delamination and contact corrosion defects is provided. A preferred embodiment comprises forming a chemical-mechanical polishing (CMP) stop layer over the surface of an inter-metal dielectric prior to forming interconnects and vias. Interconnect and vias may be formed ... 05/11/06 - 20060099788 - Injection molded metal bonding tray for integrated circuit device fabrication An injection molded metal bonding tray may be utilized in the fabrication of integrated circuit devices. In one embodiment, a substrate of an integrated circuit device is placed in a pocket of an injection molded metal bonding tray. A plurality of conductors is placed on the substrate and the conductors ... 05/11/06 - 20060099787 - Method for damascene formation using plug materials having varied etching rates Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening ... 05/11/06 - 20060099786 - Copper interconnect structure with modulated topography and method for forming the same A copper interconnect structure used in semiconductor devices includes surfaces having a surface roughness greater than 20 angstroms and which may be greater than 100 angstroms. The conformal surface of the copper interconnect structure confronts a surface roughened by ion bombardment. The copper interconnect structure is resistant to electromigration and ... 05/11/06 - 20060099785 - De-fluorination after via etch to preserve passivation Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures are capable of delivering enhanced reliability and performance due to the reduced risk ... 05/04/06 - 20060094221 - Method for manufacturing electronic device A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The ... 05/04/06 - 20060094220 - Methods of forming a metal line in a semiconductor device Methods of forming a metal line in a semiconductor device are disclosed. An illustrated method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer; ... 05/04/06 - 20060094219 - Method for manufacturing electronic device The method for manufacturing an electronic device is provided. The method includes: applying an active hydrogen species over a surface of an underlying interconnect formed on a substrate and having an anti-corrosion material formed on the surface thereof and containing copper, to remove the anti-corrosion material; and forming an insulating ... 05/04/06 - 20060094218 - Apparatus for plasma chemical vapor deposition and method for fabricating semiconductor device by using the same An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer ... 05/04/06 - 20060094217 - Method for contacting parts of a component integrated into a semiconductor substrate The invention relates to a method for contacting pans of a component integrated into a semiconductor substrate (1). According to the inventive method, a first contact hole is produced in an insulating layer (2), said contact hole being then filled with contact material (16) and connected to a line. The ... 04/27/06 - 20060088991 - Method of forming metal line in semiconductor memory device The present invention relates to a method of forming a metal line of a semiconductor memory device. According to the present invention, after a drain contact plug formed within an interlayer insulating film protrudes, a nitride film is formed on the top of the drain contact plug, and a trench ... 04/27/06 - 20060088990 - Local interconnect manufacturing process The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a ... 04/20/06 - 20060084256 - Method of forming low resistance and reliable via in inter-level dielectric interconnect A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an ... 04/06/06 - 20060073691 - Methods of manufacturing a semiconductor device In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the ... 04/06/06 - 20060073690 - Apparatus and method for metal plasma vapor deposition and re-sputter with source and bias power frequencies applied through the workpiece Physical vapor deposition and re-sputtering of a barrier layer in an integrated circuit is performed by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into said vacuum chamber. A ... 03/30/06 - 20060068578 - Manufacturing method of semiconductor device and semiconductor device A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end ... 03/30/06 - 20060068577 - Method for fabricating electrical interconnect structure A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive ... 03/16/06 - 20060057830 - Method for producing bumps on an electrical component A method for producing contacts in the form of bumps on a component that comprises a base body includes, first, positioning a template on the base body. Through holes are produced through the template. By filling the through holes with an electrically conductive material and subsequently hardening, fillers are produced. ... 03/16/06 - 20060057829 - Method of forming a damascene structure with integrated planar dielectric layers Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed ... 03/09/06 - 20060051950 - Apparatus and a method for forming an alloy layer over a substrate Embodiments of the invention involve introducing at least two metals into a chamber to form an alloy layer over a substrate. In one embodiment, at least two metals are mixed and introduced into a chamber containing a substrate and in which a focused ion beam contacts the two metals to ... 03/09/06 - 20060051949 - Semiconductor device manufacturing method and electronic equipment using same A method of manufacturing semiconductor devices includes the following steps. That is, a support board is adhered to a rear surface of a substrate proper which has a plurality of circuit element parts with prescribed functions formed on a circuit forming plane on an obverse surface thereof. First groove portions ... 03/09/06 - 20060051948 - Microprobe tips and methods for making Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include ... 03/09/06 - 20060051947 - Plasma treatment to improve barrier layer performance over porous low-k insulating dielectrics A method for plasma treating an etched opening formed in a porous low-K material to improve barrier layer integrity including providing a substrate comprising an etched opening formed in an insulating dielectric layer including porous low-K silicon oxide according to an overlying patterned resist layer; plasma treating according to a ... 03/02/06 - 20060046457 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is achieved by forming an interlayer insulating film on a conductive portion formed in a semiconductor substrate which is placed in a chamber. A contact hole is formed to pass through the interlayer insulating film to the conductive portion, and a barrier metal ... 03/02/06 - 20060046456 - Damascene process using different kinds of metals The present invention is directed to a damascene process using different kinds of metals is provided. An interlayer dielectric is formed to cover a semiconductor substrate. A contact hole is formed to expose the semiconductor substrate through the interlayer dielectric. A groove is formed to overlap the contact hole. A ... 03/02/06 - 20060046455 - Method of manufacturing electrical parts A method of manufacturing electrical parts is provided, which method comprises the steps of: forming a photoresist on a part of the surface of a substrate; forming a metal layer on the surface of the substrate after the photoresist has been formed; removing a part of the metal layer; removing ... 03/02/06 - 20060046454 - Method for filling electrically different features Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the ... 03/02/06 - 20060046453 - Method for filling electrically different features Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the ... 02/23/06 - 20060040488 - Method of electrically connecting a microelectronic component A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first ... 02/23/06 - 20060040487 - Semiconductor device, method for manufacturing the same, and plating solution The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surface of a semiconductor substrate, and also has a ... 02/23/06 - 20060040486 - Method of depositing noble metal electrode using oxidation-reduction reaction Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a noble metal layer or a noble ... 02/23/06 - 20060040485 - Method of forming via structures and method of fabricating phase change memory devices incorporating such via structures Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on ... 02/02/06 - 20060024941 - Method of forming metal interconnect of semiconductor device In a method of forming a metal interconnect of a semiconductor device using a damascene process, an etch stop layer and an insulating layer are successively formed on a semiconductor substrate, into which a conductive pattern is filled. Next, the etch stop layer and the insulating layer are patterned so ... 02/02/06 - 20060024940 - Borderless contact structures A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon ... 01/12/06 - 20060009020 - Method of forming wiring pattern A photoresist pattern is formed on an insulating substrate so that it has a reverse tapered cross section and a reverse pattern of a wiring pattern to be formed. Next, a nanoparticles-containing ink is injected on a wiring region using an inkjet system, followed by a leveling process, a drying ... 01/12/06 - 20060009019 - Methods of forming metal nitride, and methods of forming capacitor constructions The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion ... 01/05/06 - 20060003566 - Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects Methods are provided for forming semiconductor packages utilizing a device-ready wafer having a through-wafer via interconnect. One exemplary method comprises etching a via extending from a first surface of the device-ready wafer and terminating within the wafer. The first surface of the device-ready wafer is contacted with a wafer contact ... 12/29/05 - 20050287783 - Microelectronic devices and methods for forming interconnects in microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled ... 12/29/05 - 20050287782 - Methods for manufacturing a soft error and defect resistant pre-metal dielectric layer A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate ... 12/29/05 - 20050287781 - Method for interconnecting electronic components using a blend solution to from a conducting layer and an insulating layer An improved method of interconnecting electronic devices is described. In the method a blended material for forming a conducting layer and an insulating layer are deposited between a contact of a first electronic device and a second electronic device. The blended material leads to formation of a conductor overlayed by ... 12/22/05 - 20050282372 - Semiconductor device and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping ... 12/22/05 - 20050282371 - Sequential station tool for wet processing of semiconductor wafers Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for ... 12/15/05 - 20050277277 - Dual damascene process A method of photoresist processing includes forming a first photoresist layer over composite layers of dielectric insulation and a top insulating layer and patterning a via hole pattern in the first photoresist layer by exposing to radiation of a first sensitivity. A second photoresist layer is formed over via patterned ... 12/08/05 - 20050272238 - Method for depositing and etching ruthenium layers The present invention provides a method for purifying ruthenium sources to obtain high purity ruthenium metal and form a ruthenium metal pattern on a semiconductor substrate without the need for high temperature processing or a complex series of wet processes. A gas stream including ozone (O3) is brought into contact ... 12/08/05 - 20050272237 - Dual damascene integration structure and method for forming improved dual damascene integration structure Methods of densifying a porous ultra-low-k (ULK) dielectric material by using gas-cluster ion-beam processing are disclosed. Methods for gas-cluster ion-beam etching, densification, pore sealing and ashing are described that allow simultaneous removal of material and densification of the ULK interfaces. A novel ULK dual damascene structure is disclosed with densified ... 12/08/05 - 20050272236 - Method for forming bit line contact hole/contact structure Disclosed is a method for forming a bit line contact hole/contact structure. The method of the present invention comprises steps of providing a substrate; forming a pluarality of word line structures on the substrate; forming a doped dielectric layer on the substrate having the word line structures formed thereon; defining ... 11/24/05 - 20050260843 - Device and method to eliminate shorting induced by via to metal misalignment The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and ... 11/24/05 - 20050260842 - Final passivation scheme for integrated circuits A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack stop layer overlies the last level interconnect capping layer and a passivation layer overlies the buffer layer/crack stop layer. Also, a contact pad (e.g., probe ... 11/10/05 - 20050250300 - Low ohmic layout technique for mos transistors The disclosure relates to a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the ... 11/03/05 - 20050245057 - Misalignment-tolerant methods for fabricating multiplexing/demultiplexing architectures This disclosure relates to misalignment-tolerant processes for fabricating multiplexing/demultiplexing architectures. One process enables fabricating a multiplexing/demultiplexing architecture at a tolerance greater than a pitch of conductive structures with which the architecture is capable of communicating. Another process can enable creation of address elements and conductive structures having substantially identical widths. ... 10/27/05 - 20050239272 - Process for producing a multilayer arrangement having a metal layer Process for producing a multilayer arrangement having a metal layer, in which a metal layer is applied to a surface of a first wafer and at least one interlayer is applied to the metal layer. Furthermore, a second wafer is applied to the interlayer and then the first wafer is ... 10/20/05 - 20050233564 - Semiconductor device and method for fabricating the same The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The unit patterns 26c of the dummy pattern are formed in the density of 10-25%. Even in ... 10/20/05 - 20050233563 - Recess reduction for leakage improvement in high density capacitors The present invention provides a capacitor [205]. The capacitor [205] includes a first conductive layer [206] located on an interconnect structure [226] formed in a dielectric layer [228], a capacitor dielectric layer [208] located over the first conductive layer [206] and a second conductive layer [210] located over the capacitor ... 10/13/05 - 20050227471 - Post metal chemical mechanical polishing dry cleaning Metal residue on a semiconductor surface resulting from metal chemical mechanical polishing (“CMP”) process are eradicated using a dry clean process. The dry cleaning uniformly removes or substantially eliminates metal residue from the surface of the semiconductor. An unintended metal short that may be present due to the residue may ... 09/22/05 - 20050208745 - Methods of forming a conductive contact through a dielectric A dielectric is formed over a node location on a semiconductor substrate. The dielectric comprises an insulative material over the node location, an insulative polish stop layer over the insulative material, and an insulator layer over the insulative polish stop layer. A contact opening is formed into the insulator layer, ... 08/25/05 - 20050186768 - Wiring substrate produced by transfer material method A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer ... 08/18/05 - 20050181591 - Semiconductor device including mos field effect transistor having offset spacers or gate sidewall films on either side of gate electrode and method of manufacturing the same First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film ... 08/11/05 - 20050176228 - Controlled nanowire growth in permanent, integrated nano-templates and methods of fabricating sensor and transducer structures This invention presents a novel method to form uniform or heterogeneous, straight or curved and size-controllable nanostructures, nanowires, and nanotapes, including SiNW, in a nanochannel template. In the case of semiconductor nanowires, doping can be included during growth. Electrode contacts are present as needed and built in to the template ... 08/04/05 - 20050170626 - Semiconductor device and method for fabricating the device There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through ... 08/04/05 - 20050170625 - Novel method to control dual damascene trench etch profile and trench depth uniformity A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing ... 07/28/05 - 20050164481 - Method and structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via ... 07/28/05 - 20050164480 - Interface layer for the fabrication of electronic devices The present invention is directed to methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably provides Ohmic and/or rectifying contact between the active device layer and the ... 06/30/05 - 20050142833 - Method of fabricating semiconductor device The present invention provides a Cu line and method of forming the same, by which reliability (e.g., EM, BTS and the like) can be enhanced by replacing SiN by HfOx, which plays a role as a protective layer and/or an etch stop layer on a Cu line, prevents or inhibits ... 06/30/05 - 20050142832 - Method for forming dual damascene interconnection in semiconductor device A method for forming a dual damascene interconnection in a semiconductor device. An etch stop film and an intermetal insulating film are formed sequentially on a lower metal film. A via hole is formed to expose a portion of a surface of the etch stop film through the intermetal insulating ... 06/30/05 - 20050142831 - Method for forming dual damascene interconnection in semiconductor device A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected, forming ... 06/30/05 - 20050142830 - Method for forming a contact of a semiconductor device A method for forming a contact of a semiconductor device is provided, including etching a predetermined thickness of an interlayer insulating film with a first self-aligned contact (SAC) etching process, exposing an etch barrier layer with a second SAC etching process, and etching the etch barrier layer to form the ... 06/30/05 - 20050142829 - Methods for planarizing a metal layer Methods for planarizing a metal layer in a semiconductor device are disclosed. An illustrated example method comprises dividing a metal layer into a first section and a second section. A polishing removal rate associated with the first section is greater than a polishing removal rate associated with the second section. ... 06/23/05 - 20050136636 - Method for manufacturing metal structure having different heights Disclosed is a method for forming a plurality of metal structures having different heights on a semiconductor substrate. The disclosed method for manufacturing a metal structure having different heights includes: forming a plurality of seed layers, to have heights corresponding to the metal structure to be formed, on a semiconductor ... 06/23/05 - 20050136635 - Attachment of integrated circuit structures and other substrates to substrates with vias Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The ... 06/23/05 - 20050136634 - Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) ... 06/16/05 - 20050130399 - Method of forming metal line in semiconductor device A method of forming a metal line in a semiconductor device. The method includes forming an insulating interlayer over a substrate provided with a lower metal line, and forming a hole exposing the lower metal line. The method also includes forming a first metal layer on the insulating interlayer including ... ### FreshPatents.com Support |