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Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material > Insulated Gate Formation Insulated Gate FormationInsulated Gate Formation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087537 - Manufacturing method of semiconductor device A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. ... 04/19/07 - 20070087536 - Mosfet structure with multiple self-aligned silicide contacts A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface ... 03/29/07 - 20070072403 - Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device includes the steps of forming a high-k layer insulating layer on a SOI substrate; forming a gate electrode layer on the high-k insulating layer; forming a resist layer on the gate electrode layer; removing selectively the gate electrode layer using the resist layer ... 03/29/07 - 20070072402 - Method of fabricating semiconductor devices and method of removing a spacer A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on ... 03/15/07 - 20070059909 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the ... 03/15/07 - 20070059908 - Transistor design self-aligned to contact The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure (140) over a substrate (110). An insulating layer (310) is formed over the ... 03/01/07 - 20070048988 - Method for manufacturing semiconductor device using polymer A method for manufacturing a semiconductor device using a polymer is provided, wherein a first insulating layer is formed on a substrate, and a first photoresist pattern is formed over the first insulating layer. A polymer is formed around the first photoresist pattern, the polymer having an opening exposing a ... 03/01/07 - 20070048987 - Manufacturing method of semiconductor device Disclosed is a manufacturing method of a semiconductor device which comprising: preparing a substrate having a gate electrode film formed thereon and a gate insulation film formed between the substrate and the gate electrode film; and etching the gate electrode film formed on the gate insulation film of the substrate ... 02/22/07 - 20070042583 - Semiconductor device and method of manufacturing the same According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed ... 02/22/07 - 20070042582 - Method of forming a nanowire and method of manufacturing a semiconductor device using the same In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire ... 02/15/07 - 20070037372 - Planarizing a semiconductor structure to form replacement metal gates A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop. ... 02/15/07 - 20070037371 - Method of forming gate electrode structures In one example, the method includes forming a patterned hard mask feature above a layer of gate electrode material, the hard mask feature having a photoresist feature formed thereabove and the hard mask feature having a critical dimension. The method further includes performing an etching process on the patterned hard ... 02/08/07 - 20070032056 - Manufacturing method of semiconductor device This invention relates to a technology to form a polysilicon resistor having a high resistance in a semiconductor device using a silicide process. A manufacturing method of the semiconductor device of this invention includes forming an insulation film on a semiconductor substrate, forming a polysilicon film on the insulation film, ... 02/01/07 - 20070026654 - Systems and methods for avoiding base address collisions Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal ... 01/25/07 - 20070020901 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x<0.25), subjecting the first layer ... 01/25/07 - 20070020900 - Highly doped gate electrode made by rapidly melting and resolidifying the gate electrode The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode ... 01/11/07 - 20070010079 - Method for fabricating semiconductor device According to the present invention, a method for fabricating a semiconductor device includes the steps of: providing a semiconductor substrate; providing a diffusion layer in the semiconductor substrate; providing a first oxide layer on the semiconductor substrate; providing a poly-silicon layer on the first oxide layer; introducing phosphorus into the ... 12/28/06 - 20060292842 - Self-aligned gate and method A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then ... 12/14/06 - 20060281287 - Method of aligning deposited nanotubes onto an etched feature using a spacer A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched ... 12/07/06 - 20060276018 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer ... 09/07/06 - 20060199359 - Local-length nitride sonos device having self-aligned ono structure and method of manufacturing the same In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In ... 08/10/06 - 20060177998 - Fully silicided gate structure for finfet devices A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top ... 07/13/06 - 20060154459 - Manufacturing method which prevents abnormal gate oxidation A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on ... 07/06/06 - 20060148226 - Method of forming fine patterns in semiconductor device and method of forming gate using the same There are provided a method of forming fine patterns in a semiconductor device, and a method of forming a gate with a fine critical dimension using the same. In the method of forming fine patterns in a semiconductor device, a plurality of sidewall buffer patterns are formed on a gate ... 06/29/06 - 20060141757 - Method for manufacturing semiconductor device Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of preparing a semiconductor substrate, forming a buffer oxide layer, forming a hard mask layer on the buffer oxide layer, etching an exposed portion of the buffer oxide layer by using the hard mask layer, etching ... 06/22/06 - 20060134898 - Semiconductor damascene trench and methods thereof A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating ... 06/08/06 - 20060121711 - Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan ... 05/11/06 - 20060099784 - Semiconductor device manufacturing method A semiconductor device manufacturing method is provided in which, in the dummy gate pattern formation process, the pattern formation process is simplified and costs are reduced. A semiconductor device manufacturing method including: forming a mask element on a substrate; patterning the mask element into a prescribed shape, and forming a ... 05/11/06 - 20060099783 - Self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric ... 04/06/06 - 20060073689 - Method for fabricating doped polysilicon lines A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about ... 04/06/06 - 20060073688 - Gate stacks A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in ... 03/30/06 - 20060068575 - Gate electrode forming methods using conductive hard mask Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric ... 03/23/06 - 20060063364 - Method of forming a semiconductor device having a metal layer A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls ... 03/02/06 - 20060046451 - Methods of forming transistor gates; and methods of forming programmable read-only memory constructions The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive materials. The block comprises a photoresist mass and a material other than photoresist which is against the photoresist. ... 03/02/06 - 20060046450 - Semiconductor processing components and semiconductor processing utilizing same A semiconductor processing component includes a substrate and a layer overlying the substrate. The layer has a composition ReAyO1.5+2y, wherein Re is Y, La, a Lanthanoid series element, or a combination thereof, A is (Si1−aGea), 0.25≦y≦1.2, and 0≦a≦1. ... 03/02/06 - 20060046449 - Metal gate structure for mos devices A gate structure includes a gate dielectric layer disposed on a semiconductor substrate. A metal gate conductor is disposed on the gate dielectric layer. A cap layer is disposed on the metal gate conductor. At least one spacer covers sidewalls of the metal gate conductor and the cap layer, such ... 03/02/06 - 20060046448 - Facilitating removal of sacrificial layers via implantation to form replacement metal gates Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then ... 02/23/06 - 20060040482 - Mos transistor and fabrication thereof A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and ... 02/23/06 - 20060040481 - Methods and structures for preventing gate salicidation and for forming source and drain salicidation and for forming semiconductor device Methods and structures for preventing salicidation are disclosed. A substrate has an gate electrode on it. Spacers are on sidewalls of the gate electrode, exposing a top portion of the gate electrode. A dielectric layer is formed above the spacers, covering the exposed top portion of the gate electrode. Methods ... 02/16/06 - 20060035450 - Semiconductor-dielectric-semiconductor device structure fabricated by wafer bonding A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance ... 02/09/06 - 20060030136 - Method of fabricating a gate oxide layer A method of fabrication a gate oxide layer includes providing a substrate and an isolation structure on the substrate so as to isolate an active region. A spacer is formed on the sidewalls of the isolation structure. Using the isolation structure having the spacer as a mask, a dopant is ... 12/29/05 - 20050287779 - Integrated circuit structure and method of fabrication According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy ... 12/15/05 - 20050277276 - Decoupled complementary mask patterning transfer method A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning ... 12/08/05 - 20050272233 - Recessed gate electrodes having covered layer interfaces and methods of forming the same A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed. ... 12/08/05 - 20050272232 - Method for forming gate electrode of semiconductor device A method for forming a gate electrode of a semiconductor device is provided wherein a hard mask layer which is a nitride film is deposited and subjected to an additional surface deposition process so that a matrix structure of a nitride film surface becomes more compact to reduce an etching ... 12/08/05 - 20050272231 - Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a ... 11/24/05 - 20050260840 - Method of fabricating t-shaped polysilicon gate by using dual damascene process A method of fabricating a T-shaped polysilicon gate by using dual damascene process. An oxide layer, a hard mask layer, and a patterned first photoresist layer in sequence are formed on a semiconductor substrate. Using the patterned first photoresist layer as a mask, an etching process is performed on the ... 10/20/05 - 20050233562 - Method for forming a gate electrode having a metal One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of ... 10/13/05 - 20050227468 - Semiconductor device with spacer having batch and non-batch layers A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one of the plurality ... 09/29/05 - 20050215040 - Quantum wire gate device and method of making same The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride ... 09/29/05 - 20050215039 - Method and apparatus for self-aligned mos patterning A method of forming a thin film stack on a substrate, wherein the thin film stack includes at least a polysilicon layer and an oxide layer; forming a hardmask layer on the thin film stack; forming an anti-reflective coating (ARC) layer on the hardmask layer; patterning the ARC layer; etching ... 09/15/05 - 20050202662 - Method for fabricating oxide thin films A method for fabricating a thin film oxide is provided. The method includes: forming a substrate; treating the substrate at temperatures equal to and less than 360° C. using a high density (HD) plasma source; and forming an M oxide layer overlying the substrate where M is an element selected ... 09/08/05 - 20050196944 - Semiconductor device and method of manufacturing the same A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on ... 09/01/05 - 20050191832 - Novel approach to improve line end shortening A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transferred through the ARC ... 07/28/05 - 20050164478 - Novel method of trimming technology A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 ... 06/30/05 - 20050142823 - Method of fabricating gate electrode of semiconductor device A method of fabricating a gate electrode of a semiconductor device is disclosed. A disclosed method comprises growing a silicon epitaxial layer on a silicon substrate; making at least one trench through the epitaxial layer and filling the trench with a first oxide layer; etching the first oxide layer to ... ### FreshPatents.com Support |