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Semiconductor Device Manufacturing: Process > Formation Of Electrically Isolated Lateral Semiconductive Structure > Grooved And Refilled With Deposited Dielectric Material > Combined With Formation Of Recessed Oxide By Localized Oxidation Combined With Formation Of Recessed Oxide By Localized OxidationCombined With Formation Of Recessed Oxide By Localized Oxidation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.07/27/06 - 20060166459 - Semiconductor apparatus and method of producing the same the inner wall oxidizing step being performed by wet oxidization with a low concentration of moisture mixed in oxygen to form the oxide film so that a stress caused between the oxide film and the silicon substrate is not greater than 3.5×109 (dyne/cm2) and a radius at a corner of ... 05/18/06 - 20060105539 - Method of detecting etching end-point A method of detecting an etching end-point includes the steps of: forming a mask on a pattern area of an etching object; forming an etching indicator on an etching area of the etching object, which is not covered by the mask; etching the etching object using the mask; and evaluating ... 03/02/06 - 20060046428 - Trench sidewall passivation for lateral rie in a selective silicon-on-insulator process flow A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the ... 10/13/05 - 20050227452 - Method for producing semiconductor device A method for producing a semiconductor device includes the steps of forming a trench for device isolation on a silicon substrate; and annealing the silicon substrate in an atmosphere containing a noble gas at any step after the growth of a buried oxide film until the growth of a gate ... 06/23/05 - 20050136616 - Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess ... ### FreshPatents.com Support |