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Semiconductor Device Manufacturing: Process > Formation Of Electrically Isolated Lateral Semiconductive Structure > Grooved And Refilled With Deposited Dielectric Material Grooved And Refilled With Deposited Dielectric MaterialGrooved And Refilled With Deposited Dielectric Material patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087522 - Dielectric gap fill with oxide selectively deposited over silicon liner A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the ... 04/19/07 - 20070087521 - Fabrication method of semiconductor device Fabrication method of semiconductor device to reduce leak current at junction interface of p-type well and n-type well. The method comprises forming a first trench portion 109 by selective dry etching of a silicon substrate 101 using a first etching gas and forming a second trench portion 113 including an ... 04/19/07 - 20070087520 - Method for manufacturing semiconductor device A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride ... 04/19/07 - 20070087519 - Method and structure for double lining for shallow trench isolation A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer ... 04/19/07 - 20070087518 - Semiconductor device and method for producing the same A method for forming STIs in a semiconductor substrate includes forming a protective oxide film on the semiconductor substrate and forming a silicon nitride film on the protective oxide film, performing a photolithography and a dry etching so as to penetrate the silicon nitride film and the protective oxide film ... 04/19/07 - 20070087517 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includes forming a groove in the nitride ... 04/19/07 - 20070087516 - Method for forming an isolating trench with a dielectric material The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device. ... 04/19/07 - 20070087515 - Low stress sti films and methods The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less ... 04/12/07 - 20070082455 - Manufacturing method of semiconductor substrate Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming ... 04/12/07 - 20070082454 - Microelectronic device and method of manufacturing a microelectronic device A microelectronic device comprises a substrate and a transistor. The transistor comprises a channel region in the substrate, a recess in the channel region, a first dielectric layer and a second dielectric layer. The first dielectric layer comprises a first dielectric material and is deposited at the bottom of the ... 04/05/07 - 20070077724 - Etching methods and apparatus and substrate assemblies produced therewith Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma ... 04/05/07 - 20070077723 - Method of forming shallow trench isolation in a semiconductor device An exemplary method of forming a shallow trench isolation layer in a semiconductor device according to an embodiment of the present invention includes depositing a silicon nitride layer as a hard mask layer on a silicon substrate, forming a first moat pattern in the silicon nitride layer by a photolithography ... 03/29/07 - 20070072388 - Bottle-shaped trench and method of fabricating the same Fabrication of a bottle-shaped trench is disclosed. A semiconductor substrate with a trench therein is provided. An ion-doped barrier layer is formed in the trench, exposing the upper portion surfaces of the sidewall of the trench. An ion implantation is performed on the upper portion surfaces of the sidewall of ... 03/29/07 - 20070072387 - Method of fabricating shallow trench isolation structure A method of fabricating a shallow trench isolation structure is provided. A substrate having a patterned pad layer is provided. A part of the substrate is removed by using the patterned pad layer as a mask and a trench is thus formed in the substrate. A first insulation layer is ... 03/22/07 - 20070066029 - Method for fabrication of semiconductor device On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less. ... 03/22/07 - 20070066028 - Method for creating narrow trenches in dielectric materials A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance. ... 03/22/07 - 20070066027 - Method of fabricating microphone device and thermal oxide layer and low-stress structural layer thereof A substrate is provided and a plurality of trenches are formed in the front surface of the substrate. Then, a thermal oxide layer is formed on inner walls of the trenches and the front surface of the substrate. Subsequently, a first structural layer is formed on the thermal oxide layer, ... 03/22/07 - 20070066026 - Method of preventing a peeling issue of a high stressed thin film A wafer including a high stressed thin film thereon is lifted, and a pre-heating process is performed while the wafer is lifted. Subsequently, a dielectric layer is deposited on the high stressed thin film. ... 03/15/07 - 20070059899 - Sub-micron space liner and filler process A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a ... 03/15/07 - 20070059898 - Semiconductor devices including trench isolation structures and methods of forming the same Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall ... 03/15/07 - 20070059897 - Isolation for semiconductor devices Methods of forming and structures for isolation structures for semiconductor devices are disclosed. The isolation structures are wider at the bottom than at the top, providing the ability to further scale the size of semiconductor devices. A first etch process is used to form a first trench portion, and a ... 03/08/07 - 20070054464 - Different sti depth for ron improvement for ldmos integration with submicron devices An integrated circuit device having deeper STI trenches for device isolation and shallower STI trenches at the gate edge for low on-resistance and a method for forming the same are described. The integrated circuit device of the invention comprises a gate electrode on a gate dielectric layer overlying a substrate, ... 03/01/07 - 20070048966 - Narrow semiconductor trench structure Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material ... 02/22/07 - 20070042564 - Semiconductor including sti and method for manufacturing the same Provided is a semiconductor device and method of making, incorporating a trench having rounded edges. According to an embodiment, a pad oxide layer, nitride layer, and TEOS layer are sequentially formed on a substrate. The TEOS layer, nitride layer, and pad oxide layer are dry-etched using a photosensitive layer pattern ... 02/22/07 - 20070042563 - Single crystal based through the wafer connections technical field A through-the-wafer (TTW) electrically conductive connection can be produced in a heavily doped substrate. An annular trench is created from one side of the wafer such that the trench almost reaches the second side of the wafer. The annular trench can be filled with an electrically insulating material. Alternatively, an ... 02/15/07 - 20070037361 - Method for forming void-free trench isolation layer Disclosed method for forming void-free isolation comprises the steps of: forming a trench in an isolation region in a semiconductor substrate; and forming a filling oxide on the semiconductor substrate to fill the trench. The filling oxide is formed by HDP-CVD process and by using reactant gas mixture that includes ... 02/15/07 - 20070037360 - Semiconductor device using epi-layer and method of forming the same A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in ... 02/08/07 - 20070032037 - Method of forming soi-like structure in a bulk semiconductor substrate using self-organized atomic migration Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the ... 02/08/07 - 20070032036 - Array substrate for lcd and method of fabrication thereof A liquid crystal display array substrate. A trench is in a substrate. A gate, a gate dielectric layer, a semiconductor layer and a doped semiconductor layer are disposed in the trench, wherein the semiconductor layer comprises a channel. A source electrode and a drain electrode are respectively electrically connected to ... 02/01/07 - 20070026633 - Semiconductor device and related method A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation ... 02/01/07 - 20070026632 - Method of manufacturing a semiconductor device and the semiconductor device The present invention provides a method of manufacturing a trench with a rounded corner portion and a broadened opening. Anisotropic oxidation is carried out using a halogen oxidation method using dichloroethylene (DCE) to form an anisotropic oxide film such that the film thickness in a shoulder portion of the trench ... 02/01/07 - 20070026631 - Metal pad or metal bump over pad exposed by passivation layer A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed ... 02/01/07 - 20070026630 - Reliable gap-filling process and apparatus for performing the process in the manufacturing of semiconductor devices A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at ... 02/01/07 - 20070026629 - Novel structure for a multiple-gate fet device and a method for its fabrication A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form ... 02/01/07 - 20070026628 - Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or ... 01/25/07 - 20070020881 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... 01/25/07 - 20070020880 - Method of fabricating a semiconductor device and a method of generating a mask pattern At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film ... 01/25/07 - 20070020879 - Method of forming an isolation layer and method of manufacturing a field effect transistor using the same In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and ... 01/25/07 - 20070020878 - Method for fabricating a metal-insulator-metal capacitor A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substrate to form a trench ... 01/25/07 - 20070020877 - Shallow trench isolation structure and method of fabricating the same A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench. ... 01/25/07 - 20070020876 - Integrated circuitry, dynamic random access memory cells, electronic systems, and semiconductor processing methods The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having ... 01/25/07 - 20070020875 - Seamless trench fill method utilizing sub-atmospheric pressure chemical vapor deposition technique A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2O2 environment at a relatively lower temperature ranging between 500° C. and 800° ... 01/18/07 - 20070015339 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... 12/28/06 - 20060292820 - Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side ... 12/28/06 - 20060292819 - Semiconductor device and method for fabricating a semiconductor device A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the ... 12/21/06 - 20060286766 - Isolation structures for preventing photons and carriers from reaching active areas and methods of formation Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching ... 12/21/06 - 20060286765 - Method for manufacturing element isolation structural section A plurality of element forming regions and an element isolation structural section forming region which separates the plurality of element forming regions from one another, are set to a substrate. A first thermal oxide film is formed. An HfSiON film is formed. Heating processing is done. A silicon nitride film ... 12/21/06 - 20060286764 - Deposition-selective etch-deposition process for dielectric film gapfill A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the ... 12/07/06 - 20060276001 - Method for manufacturing a semiconductor device having a sti structure A method for manufacturing a STI structure includes the steps of anisotropic-etching the surface of a silicon substrate to form a trench, forming a first thermal oxide film on the surface of the trench at a substrate temperature of 1000 degrees C. or above, removing the first oxide film, anisotropic-etching ... 11/30/06 - 20060270185 - Method of forming isolation film of semiconductor device A method of forming an isolation film of a semiconductor device wherein trenches are formed by etching a semiconductor substrate using HBr and O2. Trench profiles with a slope can be formed, ISO gap fill can be facilitated, and voids are not generated. Accordingly, the invention is advantageous in that ... 11/30/06 - 20060270184 - Method of forming trench type isolation film of semiconductor device A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning the nitride film ... 11/30/06 - 20060270183 - Isolation structure and method of forming the same An isolation structure may include a trench formed on a surface of a substrate. A first isolation pattern may be provided on an inner face of the trench to define an auxiliary trench. A second isolation pattern may be provided on the first isolation pattern to partially fill the auxiliary ... 11/30/06 - 20060270182 - Manufacturing process of semiconductor device and semiconductor device A manufacturing process of a semiconductor device, includes: forming a ground oxide film, which includes over a well region of a first conductive type, on a silicon semiconductor substrate; forming a nitride film over the ground oxide film; forming a mask pattern by selectively etching the nitride film and the ... 11/30/06 - 20060270181 - Methods of forming integrated circuit devices Forming an integrated circuit device includes forming a hard mask layer overlying a semiconductor substrate. The hard mask layer is patterned to expose portions of the substrate and edges of the hard mask layer. Exposed portions of the substrate are removed. A first portion of the substrate is covered with ... 11/23/06 - 20060264003 - Trench isolation structure in a semiconductor device and method for fabricating the same A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewall oxide film is formed overlying the first trenches. A first ... 11/16/06 - 20060258119 - Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer ... 11/16/06 - 20060258118 - Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer ... 11/16/06 - 20060258117 - Dry etching method, fabrication method for semiconductor device, and dry etching apparatus When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application ... 11/16/06 - 20060258116 - Shallow trench isolation A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a ... 11/16/06 - 20060258115 - Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, forming a film containing impurities on an inner surface of a lower part of the trench, forming a silicon nitride film so that an upper sidewall of the trench is covered by the silicon nitride ... 11/09/06 - 20060252228 - Shallow trench isolation structure having reduced dislocation density A method for manufacturing a shallow trench isolation structure comprises etching a plurality of trenches into a silicon substrate. The trenches have an upright wall portion, a bottom floor portion, and a corner portion connecting the upright wall portion and the bottom floor portion. The method further comprises conformally depositing ... 11/02/06 - 20060246683 - Integrated equipment set for forming a low k dielectric interconnect on a substrate A method is provided that includes (1) receiving information about a substrate processed within a low K dielectric deposition subsystem from an integrated inspection system of the low K dielectric deposition subsystem; (2) determining an etch process to perform within an etch subsystem based at least in part on the ... 11/02/06 - 20060246682 - Product and method for integration of deep trench mesh and structures under a bond pad A method of integrating circuit components under bond pads includes establishing a trench border on a circuit element and synthesizing a set of trench mesh edges of a trench mesh to be coincident with the trench border on the circuit element. The method further includes eliminating a trench mesh contained ... 10/26/06 - 20060240637 - Methods of forming semiconductor constructions The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature ... 10/26/06 - 20060240636 - Trench isolation methods of semiconductor device In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A ... 10/26/06 - 20060240635 - Self-aligned sti sonos Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer ... 10/19/06 - 20060234470 - Process sequence for doped silicon fill of deep trenches A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way ... 10/19/06 - 20060234469 - A method of forming semiconductor structures In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) ... 10/19/06 - 20060234468 - Method for manufacturing a semiconductor device, as well as a semiconductor substrate A method for manufacturing a semiconductor device, includes: forming a recognition mark that defines a well-forming region for forming a well on a semiconductor substrate; forming a mask, using the recognition mark, that is patterned so that the well-forming region is opened; introducing an impurity into the well-forming region; performing ... 10/19/06 - 20060234467 - Method of forming trench isolation in a semiconductor device Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during ... 10/05/06 - 20060223278 - Non-critical complementary masking method for poly-1 definition in flash memory device fabrication A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of ... 09/21/06 - 20060211215 - Semiconductor device and method of manufacturing the same Included are steps of: selectively etching a nitride film and a thermal oxide film in a thick gate insulating film forming region of a silicon substrate on which the thermal oxide film is formed with the nitride film formed on the thermal oxide film, and in which a trench with ... 09/21/06 - 20060211214 - Method of manufacturing a semiconductor device Even though photolithography with a diameter of 0.20 μm or less is employed, a contact hole having a tapered shape with a required width including a positioning tolerance can be formed in a narrower gap between the gate electrodes. A method forms a minute contact hole between gate electrodes of ... 09/21/06 - 20060211213 - Method of manufacturing semiconductor device having step gate Disclosed herein is a method of manufacturing a semiconductor device having a step gate, which can improve the refresh characteristics of the device. The method comprises the steps of: forming on a silicon substrate having active and field regions a first hard mask exposing the field region; etching the exposed ... 09/14/06 - 20060205173 - Methods for forming isolation films A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a ... 09/07/06 - 20060199352 - Method of manufacturing shallow trench isolation structure A method of manufacturing a shallow trench isolation structure adapted for a substrate, is provided. A dielectric film is formed on the substrate and then a buffer layer having a first thickness is formed on the dielectric film. Then, a hard mask layer having a second thickness is formed on ... 08/31/06 - 20060194410 - Semiconductor device with cavity and method of manufacture thereof A semiconductor device is provided with a substrate with a cavity inside, the substrate including a device formation area located above the cavity, a plurality of trenches formed in the substrate to communicate with the cavity and surround the device formation area, and an oxide film formed around each of ... 08/31/06 - 20060194409 - Process for manufacturing a soi wafer with improved gettering capability Manufacturing of a wafer made of semiconductor material on insulator including the steps of: providing a composite wafer having a substrate, an insulating layer and an active layer of semiconductor material, arranged on top of one another; forming at least one deep trench within the active layer of the composite ... 08/24/06 - 20060189092 - Manufacturing method of semiconductor device with filling insulating film into trench Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first ... 08/17/06 - 20060183296 - Isolation method for semiconductor device An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask ... 08/17/06 - 20060183295 - Semiconductor device having self-aligned contact and manufacturing method thereof A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on ... 08/17/06 - 20060183294 - Methods of forming integrated circuitry The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of isolation trenches within semiconductive silicon-comprising material. The isolation trenches comprise sidewalls comprising exposed semiconductive silicon-comprising material. An epitaxial silicon-comprising layer is grown from the exposed semiconductive silicon-comprising ... 07/27/06 - 20060166458 - Method for forming shallow trench isolation structures A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate. The polish stop layer may be nitride. An opening is formed extending through the deposited silicon layer and the nitride ... 07/20/06 - 20060160326 - Method for rounding top corners of isolation trench in semiconductor device A method for forming an isolation trench in a semiconductor device includes the steps of: forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a photoresist pattern defining an isolation area on the pad nitride layer; forming a trench ... 07/20/06 - 20060160325 - Method of manufacturing semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an insulation layer on a silicon substrate; forming a shallow trench isolation (STI) pattern by a photolithography and etching process; forming a high density plasma (HDP) oxide layer on the STI pattern; ... 07/20/06 - 20060160324 - Deglaze route to compensate for film non-uniformities after sti oxide processing A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct ... 07/20/06 - 20060160323 - Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer ... 07/20/06 - 20060160322 - Nitridation of sti fill oxide to prevent the loss of sti fill oxide during manufacturing process A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride ... 07/20/06 - 20060160321 - Method of forming trench isolation structure There is provided a method for trench isolation structure formation, which produces neither voids nor cracks within a groove. This method comprises the steps of: forming a groove on a surface of a silicon substrate; coating a polysilazane solution; prebaking the coating at a prebaking temperature regulated so that the ... 07/13/06 - 20060154439 - Method of fabricating semiconductor device In a method of fabricating a semiconductor device, trenches are formed defining active regions at predetermined portions of a semiconductor substrate. A thermal oxide layer and a liner layer are sequentially formed covering inner walls of the trenches and upper surfaces of the active regions. Device isolation patterns are formed ... 07/13/06 - 20060154438 - Method for manufacturing semiconductor device with trenches in substrate surface In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on ... 07/06/06 - 20060148206 - Valve operating assembly and method of manufacturing The present invention relates to a leakdown plunger, comprising a first plunger opening, a second plunger opening, and an outer plunger surface that is provided with an axis and encloses an inner plunger surface, the first plunger opening is provided with a first annular plunger surface shaped to accommodate a ... 07/06/06 - 20060148205 - Semiconductor manufacturing method for device isolation Provided is a manufacturing step of an element isolation by forming an isolation trench in an element isolation region of a semiconductor substrate, forming an HDP film over the semiconductor substrate including the inside of the isolation trench, and then polishing the HDP film by CMP to remove the HDP ... 07/06/06 - 20060148204 - Monitoring pattern for optimization of chemical mechanical polishing process of trench isolation layer and related methods A monitoring pattern includes unique active area arrays, each having at least two active areas separated and defined by a trench isolation area filled with a trench isolation layer. Each active area array differs from the others in shape, size, spaced distance, extending direction, and/or density. In a monitoring method, ... 07/06/06 - 20060148203 - Semiconductor device and fabricating method thereof A semiconductor device and fabricating method thereof are provided. A dual gate oxide layer is formed by thermal oxidation after carrying out a prescribed pre-processing on an STI edge, which results in a high quality oxide layer by thermal oxidation and a uniformly maintained gate oxide layer thickness of a ... 07/06/06 - 20060148202 - Method for forming shallow trench isolation in semiconductor device A method for forming shallow trench isolation in a semiconductor device including forming a pad oxide, a pad nitride, and a pore-generating layer on an entire surface of a semiconductor substrate in successive order; etching the pore-generating layer, the pad nitride, the pad oxide and the substrate to form a ... 07/06/06 - 20060148201 - Method for forming an sti in a flash memory device The present invention provides a method of forming an STI region in a flash memory device. The method includes: forming a pad oxide layer on a semiconductor substrate; forming a hard mask on the pad oxide layer; forming a recess groove below the hard mask by etching a portion of ... 07/06/06 - 20060148200 - Method of forming isolation oxide layer in semiconductor integrated circuit device A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second ... 07/06/06 - 20060148199 - Method for fabricating semiconductor device A method for fabricating a semiconductor device includes the steps of sequentially forming a pad oxide layer and a pad nitride layer on a substrate, the pad oxide layer including a first oxide layer formed on an upper surface of the substrate and a second oxide layer formed on a ... 07/06/06 - 20060148198 - Method for forming device isolation region in semiconductor device An exemplary method of forming a device isolation region in a semiconductor device according to an embodiment of the present invention includes forming a sacrificial layer and a hard mask on a substrate; selectively etching the hard mask, the sacrificial layer, and the substrate so as to form a trench; ... 07/06/06 - 20060148197 - Method for forming shallow trench isolation with rounded corners by using a clean process In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a ... 07/06/06 - 20060148196 - Semiconductor fabrication process including recessed source/drain regions in an soi wafer A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is ... 06/29/06 - 20060141741 - Adjuvant for chemical mechanical polishing slurry Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms a adsorption layer on the cationically charged material in order to increase the polishing selectivity of the anionically charged material to cationically charged material, wherein the adjuvant comprises a ... 06/29/06 - 20060141740 - Semiconductor device with shallow trench isolation and a manufacturing method thereof An exemplary method of manufacturing a shallow trench isolation structure in a semiconductor device includes forming a first trench region by etching the semiconductor substrate to a predetermined depth, forming a first oxide layer on the entire surface of the semiconductor substrate so as to fill the first trench region, ... 06/29/06 - 20060141739 - Method for fabricating contact holes in a semiconductor body and a semiconductor structure A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes are electrically insulated from the semiconductor body by ... 06/22/06 - 20060134882 - Method to improve device isolation via fabrication of deeper shallow trench isolation regions A method of forming a shallow trench isolation (STI) structure wherein the depth of the STI structure has been extended via formation of an underlying silicon oxide region, has been developed. After definition of a shallow trench isolation shape in a top portion of a semiconductor substrate a self-aligned ion ... 06/22/06 - 20060134881 - Method of forming trench isolation device capable of reducing corner recess A method of forming a trench isolation device capable of reducing corner recess comprising forming a pad oxide layer and a silicon nitride mask layer on a semiconductor base, and forming a trench by etching. Next, a liner oxide layer is formed on the semiconductor base and on the surface ... 06/15/06 - 20060128114 - Trench isolation type semiconductor device and method of fabricating the same A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed ... 06/15/06 - 20060128113 - Technique and methodology to passivate inductively or capacitively coupled surface currents under capacitor structures A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch ... 06/15/06 - 20060128112 - Technique and methodology to passivate inductively coupled surface currents A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch ... 05/25/06 - 20060110891 - Method for rounding bottom corners of trench and shallow trench isolation process A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench. ... 05/11/06 - 20060099771 - Selective nitride liner formation for shallow trench isolation A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said ... 05/04/06 - 20060094203 - Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so ... 05/04/06 - 20060094202 - Semiconductor array and method for manufacturing a semiconductor array A process for manufacturing a semiconductor array, wherein a trench structure is introduced into a first monocrystalline semiconductor region, the trench structure is filled with an insulator, whereby a number of layers of the insulator together have a heat conductance greater than 20 W/mK, an amorphous silicon layer, which is ... 05/04/06 - 20060094201 - Method for forming isolation film in semiconductor device A method for forming an isolation film of a semiconductor device is disclosed which includes forming trenches in a semiconductor substrate, forming a first HDP oxide film in the formed trenches, performing an etch-back process using a mixing gas of C2F6 gas and O2 gas to form vertical walls in ... 05/04/06 - 20060094200 - Methods for controlling feature dimensions in crystalline substrates A method of forming a slot in a substrate comprises growing an oxide layer on a first side of a substrate, patterning and etching the oxide layer to form an opening, forming a material overlying the opening and the oxide layer, removing substrate material through a second side to a ... 04/27/06 - 20060088977 - Method of forming an isolation layer in a semiconductor device Disclosed herein is a method of forming an element isolation film of a semiconductor device. An aluminum oxide film of a high wet etch rate is used as a pad oxide film, a trench is formed, and top and bottom edges of the trench is made rounded while removing some ... 04/27/06 - 20060088976 - Methods and compositions for chemical mechanical polishing substrates Methods and compositions are provided for planarizing a substrate surface with reduced or minimal defects in surface topography. In one aspect, a method is provided for processing a substrate comprising a dielectric material and polysilicon material disposed thereon, polishing the polysilicon material with a high topography selective polishing composition, and ... 03/30/06 - 20060068562 - Trench isolation structure and method of manufacture therefor The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask over a substrate, etching a trench in the substrate through the hardmask, ... 03/23/06 - 20060063350 - Semiconductor constructions The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory ... 03/23/06 - 20060063349 - Method of forming a shallow trench-deep trench isolation region for a bicmos/cmos technology A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided. ... 03/16/06 - 20060057816 - Sensor element with trenched cavity A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an access hole and a buried cavity, at least one ... 03/09/06 - 20060051932 - Semiconductor device and method for manufacturing semiconductor device A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type ... 03/09/06 - 20060051931 - Method for fabricating a trench isolation structure having a high aspect ratio A method for fabricating a trench isolation structure wherein a trench is formed in a silicon body and an oxide layer is formed in the trench. The silicon body is exposed at the bottom of the trench by means of an etching step, and silicon oxide is selectively grown on ... 03/09/06 - 20060051930 - Method for forming isolation layer in semiconductor memory device Disclosed herein is a method for forming an isolation film of a semiconductor memory device. According to the disclosure, in a pre-treatment cleaning process performed before a tunnel oxide film is formed, a SC-1 cleaning process is performed at a temperature ranging from 60° C. to 70° C. Therefore, oxide ... 03/09/06 - 20060051929 - Electrical properties of shallow trench isolation materials via high temperature annealing in the presence of reactive gases The present invention relates to semiconductor device fabrication and more specifically to a method and material for forming high density shallow trench isolation structures in integrated circuits having improved electrical properties. A silica dielectric film is formed on a substrate (a) preparing a composition comprising a silicon containing pre-polymer, a ... 03/02/06 - 20060046427 - Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate. The method includes flowing a silicon-containing precursor into a process chamber housing the substrate, flowing an oxidizing gas into the chamber, and providing a hydroxyl-containing precursor in the process chamber. The method also ... 03/02/06 - 20060046426 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... 03/02/06 - 20060046425 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... 03/02/06 - 20060046424 - Methods of forming semiconductor constructions The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory ... 02/23/06 - 20060040464 - Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, ... 02/23/06 - 20060040463 - Manufacturing method of an electronic part built-in substrate A manufacturing method of an electronic part built-in substrate is disclosed, wherein an electronic part is contained in a build-up layer, the manufacturing method including a step for arranging an electronic part on a conductive supporting object such that the electronic part is electrically connected to the conductive supporting object, ... 02/23/06 - 20060040462 - Novel method to improve sram performance and stability A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps ... 02/16/06 - 20060035437 - Semiconductor device having dual-sti and manufacturing method thereof A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a ... 02/09/06 - 20060030119 - Method of manufacturing semiconductor device There has heretofore been a problem that a junction leak current between a collector and a base is generated by a crystal defect caused in an end portion of a groove adjacent to a base region. In the present invention, an opening is formed in a silicon oxide film and ... 02/09/06 - 20060030118 - Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolation material A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an ... 02/02/06 - 20060024914 - Wet etching method of removing silicon from a substrate and method of forming trench isolation A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for ... 02/02/06 - 20060024913 - Methods for manufacturing shallow trench isolation layers of semiconductor devices A method for forming a shallow trench isolation layer that includes: forming a pad oxide on a substrate; forming a hard mask silicon nitride on the pad oxide; forming a moat pattern on the pad oxide and hard mask; etching partially the pad oxide and hard mask with the moat ... 02/02/06 - 20060024912 - Method for manufacturing device isolation film of semiconductor device A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap ... 02/02/06 - 20060024911 - Method to design for or modulate the cmos transistor inverse narrow width effect (inwe) using shallow trench isolation (sti) A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the ... 02/02/06 - 20060024910 - Method to engineer the inverse narrow width effect (inwe) in cmos technology using shallow trench isolation (sti) A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation ... 02/02/06 - 20060024909 - Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate ... 01/19/06 - 20060014361 - Method for forming device isolation layer of semiconductor device A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined thickness by using the moat pattern, forming ... 01/19/06 - 20060014360 - Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device includes forming a coating type carbon film on a semiconductor substrate, patterning the coating type carbon film according to trenches formed in the semiconductor substrate and having different opening widths, and etching the semiconductor substrate with the patterned coating type carbon film serving ... 01/19/06 - 20060014359 - Formation of active area using semiconductor growth process without sti integration A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. ... 01/12/06 - 20060009004 - Method of forming trench isolation within a semiconductor substrate A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch ... 01/05/06 - 20060003544 - Methods of forming trench isolation regions The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to ... 01/05/06 - 20060003543 - Methods of forming trench isolation regions The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to ... 01/05/06 - 20060003542 - Method of oxidizing object to be processed and oxidation system A method of oxidizing an object to be processed comprises the steps of: providing an object to be processed W having a groove 4 formed on its surface in a processing vessel 22 capable of forming a vacuum therein, oxidizing the surface of the object to be processed in an ... 01/05/06 - 20060003541 - Method for forming device isolation film of semiconductor device A method for forming device isolation film of semiconductor device is provided, the method including sequentially forming a pad oxide layer and a pad nitride layer on a semiconductor substrate having a cell region and a peripheral circuit region, etching a predetermined region of the pad nitride layer, the pad ... 01/05/06 - 20060003540 - Marker for alignment of non-transparent gate layer, method for manufacturing such a marker, and use of such a marker in a lithographic apparatus A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is ... 12/29/05 - 20050287764 - Method of fabricating shallow trench isolation by ultra-thin simox processing The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen ... 12/29/05 - 20050287763 - Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial ... 12/29/05 - 20050287762 - Formation of removable shroud by anisotropic plasma etch Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant ... 12/29/05 - 20050287761 - Method for fabricating a capacitor in a semiconductor device A method for fabricating a capacitor in a semiconductor device that includes providing a semiconductor substrate, forming at least one shallow trench isolation structure in the semiconductor substrate, forming a tunnel oxide layer over the semiconductor substrate, depositing a first polysilicon layer over the tunnel oxide layer, depositing a nitride ... 12/22/05 - 20050282352 - Method of forming dual gate dielectric layer A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region, ... 12/22/05 - 20050282351 - Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench ... 12/22/05 - 20050282350 - Atomic layer deposition for filling a gap between devices A method is provided for filling a trench or gap between a pair of semiconductor devices formed above a substrate. A liner is applied in a trench or gap between a pair of devices by atomic layer deposition to partially fill the trench or gap. The trench or gap is ... 12/15/05 - 20050277263 - Forming shallow trench isolation without the use of cmp Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so ... 12/01/05 - 20050266654 - Barrier to amorphization implant A method includes forming a first and a second semiconductor region which are joined at a semiconductor junction. The first and second semiconductor regions are truncated with an isolation trench, with an end of the semiconductor junction being disposed at the isolation trench. The isolation trench is at least partially ... 11/24/05 - 20050260825 - Shallow trench isolation structure for strained si on sige A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into ... 11/17/05 - 20050255668 - Method of fabricating shallow trench isolation structure A method of fabricating a shallow trench isolation (STI) structure is provided. A pad oxide layer, a pad silicon layer and a mask layer are sequentially formed over a substrate. Thereafter, the mask layer and the pad silicon layer are patterned to form an opening that exposes a portion of ... 11/10/05 - 20050250293 - Method for fabricating semiconductor device having trench isolation Disclosed is a method for fabricating a semiconductor device capable of preventing a depth of a plurality of moats M from getting deeper as preventing lowering a threshold voltage by forming a round shape of a top corner of a trench. Particularly, the method includes the steps of: forming a ... 11/03/05 - 20050245044 - Methods of forming semiconductor constructions The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within the center region, and openings within the edge region. While the substrate ... 11/03/05 - 20050245043 - Method of fabricating an integrated circuit including hollow isolating trenches and corresponding integrated circuit A method is provided for fabricating an integrated circuit. According to the method, hollow isolating trenches are produced within a substrate, and active components are produced in and on active areas of the substrate that are between the trenches. The trenches are produced in an initial phase carried out before ... 11/03/05 - 20050245042 - Fabrication method for a semiconductor structure The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step ... 11/03/05 - 20050245041 - Technique for reducing the roughness of metal lines in a metallization layer A simplified dielectric layer stack for the first metallization layer is provided in combination with an improved anisotropic etch process, wherein the etch attack at the trench perimeter is reduced for a patterning process on the basis of a 193 nm lithography. In the simplified layer stack, a bottom low-k ... 10/27/05 - 20050239265 - Method of forming trench isolation regions In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of ... 10/27/05 - 20050239264 - Materials suitable for shallow trench isolation The invention relates to semiconductor device fabrication and more specifically to a method and material for forming of shallow trench isolation structures in integrated circuits. A silica dielectric film is formed by preparing a composition comprising a silicon containing pre-polymer, optionally water, and optionally a metal-ion-free catalyst selected from the ... 10/20/05 - 20050233541 - Semiconductor device having dual isolation structure and method of fabricating the same In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined by a device isolation layer. The device isolation ... 10/20/05 - 20050233540 - Minimizing transistor variations due to shallow trench isolation stress Other embodiments of the present invention include a MOS transistor device (200) and a process (300) for constructing an integrated circuit. ... 10/13/05 - 20050227451 - Chemical mechanical polishing aqueous dispersion and chemical mechanical polishing method Disclosed is a chemical mechanical polishing aqueous dispersion comprising (A1) first fumed silica having a specific surface area of not less than 10 m2/g and less than 160 m2/g and an average secondary particle diameter of not less than 170 nm and not more than 250 nm and (A2) second ... 10/13/05 - 20050227450 - Methods of forming trench isolation regions The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to ... 10/06/05 - 20050221579 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate and first and second trenches. The first trench with a high aspect ratio is formed in a surface of the semiconductor substrate and has a bottom, two sidewalls and an open end. The first trench is formed so that at the bottom side, ... 10/06/05 - 20050221578 - Semiconductor device with shallow trench isolation and method of fabricating the same A semiconductor device includes a semiconductor substrate having an upper surface, a trench formed in the semiconductor substrate, a first insulating film formed on the semiconductor substrate so as to be located at opposite sides of the trench, a polycrystalline silicon film stacked on the first insulating film, the polycrystalline ... 09/29/05 - 20050215027 - Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes ... 09/29/05 - 20050215026 - Method for producing semiconductor device With respect to nitriding of an oxide film on an inner wall of a trench, a method for producing a semiconductor device is provided, the method preventing the characteristic deterioration of the semiconductor device by controlling and optimizing peak nitrogen concentration in an oxide film to reduce the stress and ... 09/22/05 - 20050208729 - Methods of forming a double-sided capacitor or a contact using a sacrificial structure and semiconductor device precursor structures to a double-sided capacitor or a contact A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over ... 09/01/05 - 20050191823 - Polishing composition and polishing method A polishing composition includes more than 0.1% by mass of colloidal silica, and water, and has a pH of 6 or less. The polishing composition has the ability to polish a titanium material at a high stock removal rate. Thus, the polishing composition is suitable for use in applications for ... 09/01/05 - 20050191822 - Shallow trench isolation method for a semiconductor wafer The present invention relates to a shallow trench isolation method of a semiconductor wafer. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench. ... 08/25/05 - 20050186756 - Method of forming alignment marks for semiconductor device fabrication A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film ... 08/25/05 - 20050186755 - Sub-micron space liner and densification process A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a ... 08/11/05 - 20050176214 - Method of forming a shallow trench-deep trench isolation region for a bicmos/cmos technology A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized ... 08/04/05 - 20050170607 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multilayered film containing the silicon nitride oxide film on the silicon nitride film; ... 08/04/05 - 20050170606 - Method of achieving improved sti gap fill with reduced stress A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least ... 07/28/05 - 20050164468 - Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region ... 07/21/05 - 20050158965 - Methods for filling high aspect ratio trenches in semiconductor layers Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The ... 07/21/05 - 20050158964 - Method of forming an sti feature to avoid electrical charge leakage A method for forming shallow trench isolation (STI) structure including providing a substrate comprising an overlying hardmask layer; patterning the hardmask layer to form a hardmask layer opening for etching a trench through a substrate thickness portion; etching a trench according to the patterned overlying hardmask layer; carrying out a ... 07/21/05 - 20050158963 - Method of forming planarized shallow trench isolation Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and ... 07/14/05 - 20050153521 - Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element ... 07/14/05 - 20050153520 - Method for manufacturing semiconductor device The present invention discloses a method for forming an element isolation film of a semiconductor device, comprising the steps of: sequentially forming a pad oxide film, a pad nitride film and a mask oxide film on a semiconductor substrate on which a first region for forming a high voltage device ... 07/14/05 - 20050153519 - Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to ... 07/07/05 - 20050148155 - Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a ... 07/07/05 - 20050148154 - Semiconductor device and manufacturing method therefor A semiconductor device having a trench element separation region is disclosed. A pad oxide film (2), and a silicon nitride film (3) may be formed on a semiconductor substrate (1). A trench (4) may be formed by dry etching using the silicon nitride film (3) as a mask. The silicon ... 07/07/05 - 20050148153 - Method of dry etching semiconductor device A silicon oxide film (12) and a silicon nitride film (13) are sequentially formed over a silicon substrate (11) having a plane orientation (100). A trench (14) is formed with the patterned silicon nitride (13) as a mask. Argon is ion-implanted from the direction normal to a plane orientation (111) ... 07/07/05 - 20050148152 - Method for forming shallow trench in semiconductor device Disclosed is a method for forming a shallow trench. The method of the present invention comprises steps of providing a substrate; forming a plurality of operation layers on the substrate; forming photoresist on the uppermost one of the operation layers to define a position to be etched; etching a portion ... 06/30/05 - 20050142807 - Differential pressure application apparatus for use in polishing layers of semiconductor device structures and method An apparatus for applying different amounts of pressure to different locations of a semiconductor device structure or other substrate during polishing thereof. The apparatus is configured to be associated with a wafer carrier of a polishing apparatus and includes pressurization structures configured to individually apply pressure to a major surface ... 06/30/05 - 20050142806 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is disclosed. In the method, a buffer oxide film and a nitride film are formed on a semiconductor substrate in succession, an opening is formed in the nitride film and the buffer oxide film for exposing a field region of the semiconductor substrate, ... 06/30/05 - 20050142805 - Methods for fabricating an sti film of a semiconductor device Methods for fabricating a shallow trench isolation (STI) of a semiconductor device are disclosed. A disclosed method includes: forming a trench on a semiconductor substrate, forming an oxide layer on the semiconductor substrate and the trench, forming a photoresist pattern on the oxide layer exposing the oxide layer on a ... 06/30/05 - 20050142804 - Method for fabricating shallow trench isolation structure of semiconductor device A method for fabricating a shallow trench isolation structure of semiconductor device is disclosed. The method for fabricating a shallow trench isolation structure of semiconductor device comprises growing a silicon oxide layer on a substrate, depositing a nitride layer with a predetermined thickness and growing a thermal oxide layer as ... |