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Semiconductor Device Manufacturing: Process > Formation Of Electrically Isolated Lateral Semiconductive Structure Formation Of Electrically Isolated Lateral Semiconductive StructureFormation Of Electrically Isolated Lateral Semiconductive Structure patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/29/07 - 20070072386 - Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same A method of forming an alignment key with a capping layer in a semiconductor device without an additional mask formation process, and a method of fabricating a semiconductor device using the same, may be provided. The method of forming an alignment key may include forming an isolation layer confining an ... 03/08/07 - 20070054463 - Method for forming spacers between bitlines in virtual ground memory array and related structure According to one exemplary embodiment, a method of fabricating a virtual ground memory array, which includes bitlines situated in a substrate, includes forming at least one recess in the substrate between two adjacent bitlines, where the at least one recess is situated in a bitline contact region of the virtual ... 02/22/07 - 20070042560 - Method for growing thin nitride film onto substrate and thin nitride film device The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low temperature process. In the method for growing the thin nitride film over a substrate, ... 01/18/07 - 20070015338 - Substrate applicable to both wire bonding and flip chip bonding, smart card modules having the substrate and methods for fabricating the same A substrate, a smart card module having the substrate and methods for fabricating the same are provided. A substrate having metal patterns formed on both sides and applicable to both wire bonding and flip chip bonding, a smart card module having the same and methods of fabricating the same are ... 11/30/06 - 20060270178 - Method for manufacturing high-frequency signal transmission circuit and high-frequency signal transmission circuit device A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first ... 11/09/06 - 20060252227 - Sram cell having stepped boundary regions and methods of fabrication A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active ... 11/09/06 - 20060252226 - Integrated soi fingered decoupling capacitor The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ ... 11/09/06 - 20060252225 - Method to create a metal pattern using a damascene-like process and associated structures A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material. A conformed metal layer is formed over the dielectric layer and into the at least one trench and a photoresist layer is ... 11/02/06 - 20060246680 - Stable pd-soi devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes ... 10/26/06 - 20060240634 - Dram access transistor and method of formation Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions ... 10/12/06 - 20060228864 - Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using epi-si growth process A semiconductor device having a transistor and a storage capacitor. The transistor includes source and drain regions formed on a substrate. The storage capacitor is coupled to the transistor. The storage capacitor is formed from a bottle-shaped trench and having an Epi-Si layer grown inside the trench to form at ... 10/05/06 - 20060223277 - Method of manufacturing a semiconductor memory device A method of manufacturing a semiconductor device comprises providing a semiconductor substrate, forming trenches in predetermined regions of the semiconductor substrate, forming isolation structures within the trenches that separate active regions and field regions of the device, and etching exposed regions of the semiconductor substrate so that the exposed regions ... 09/28/06 - 20060216903 - Building fully-depleted and bulk transistors on same chip A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and bulk transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed. ... 08/31/06 - 20060194405 - Semiconductor device and method of fabricating the same A semiconductor device has an element isolating region formed of an insulating film having etching rates different from each other in a side close to an inside wall and a center side of a trench formed on a semiconductor substrate, and a selective epitaxial layer formed in both sides of ... 08/17/06 - 20060183292 - Sti liner modification method A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of ... 08/10/06 - 20060177989 - Substrate before insulation, method of manufacturing substrate, method of manufacturing surface acoustic wave transducer, surface acoustic wave device, and electronic equipment A substrate before an insulation process, which is provided with a protection film to prevent a part of a surface area, which has electrical conductivity from being insulated, the substrate comprises: a base including the surface area, which has electrical conductivity; a protection film covering over the part of the ... 07/27/06 - 20060166457 - Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits A method for manufacturing a semiconductor wafer 10 that includes implanting source/drain regions 75 within a top surface of the semiconductor substrate 20, forming a dielectric capping layer 170 over the semiconductor wafer 20, and annealing the semiconductor wafer 10 to activate sources/drains 70. The method further includes forming a ... 06/15/06 - 20060128111 - Raised sti process for multiple gate ox and sidewall protection on strained si/sgoi structure with elevated source/drain The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric ... 06/15/06 - 20060128110 - Semiconductor device and a method of manufacturing the same A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an ... 06/01/06 - 20060115955 - Method for manufacturing anti-punch through semiconductor device A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers ... 05/11/06 - 20060099770 - Semiconductor article and method for manufacturing the semiconductor article A method for manufacturing a semiconductor article and a semiconductor article is provided, wherein a base region of a first semiconductor material is applied, a silicide layer is applied above the base region, after the application of the silicide layer, an opening is created in the suicide layer by removing ... 03/30/06 - 20060068561 - Semiconductor device and method for manufacturing thereof A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the ... 01/26/06 - 20060019462 - Patterned strained semiconductor substrate and device A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive ... 12/29/05 - 20050287759 - Method and apparatus for a semiconductor device with a high-k gate dielectric A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric ... 12/08/05 - 20050272220 - Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications A UV curing process for a dielectric material used in pre-metal and shallow trench isolation applications comprises coating a suitable dielectric material onto a substrate; and exposing the dielectric material to ultraviolet radiation in an amount effective to reduce an organic content and/or increase a density and./or increase a wet ... 11/17/05 - 20050255665 - Manufacturing method of a contact structure and phase change memory cell with elimination of double contacts The method forms a phase change memory cell with a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second ... 10/20/05 - 20050233539 - Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to ... 09/08/05 - 20050196933 - Single crystal silicon sensor with additional layer and method of producing the same A SOI-based MEMS device has a base layer, a device layer, and an insulator layer between the base layer and the device layer. The device also has a deposited layer having a portion that is spaced from the device layer. The device layer is between the insulator layer and the ... 07/28/05 - 20050164467 - Semiconductor device and a method of manufacturing the same Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is ... 06/30/05 - 20050142795 - Method for isolating semiconductor devices with use of shallow trench isolation method The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first ... ### FreshPatents.com Support |