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Semiconductor Device Manufacturing: Process > Forming Bipolar Transistor By Formation Or Alteration Of Semiconductive Active Regions > Self-aligned > Dopant Implantation Or Diffusion Dopant Implantation Or DiffusionDopant Implantation Or Diffusion patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/01/07 - 20070048958 - Three-dimensional multi-gate device and fabricating method thereof A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the ... 11/09/06 - 20060252217 - Non-uniform ion implantation apparatus and method thereof A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ... 08/31/06 - 20060194401 - Method for manufacturing a semiconductor device having an alignment feature formed using an n-type dopant and a wet oxidation process The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further ... 07/27/06 - 20060166452 - Non-volatile nanocrystal memory and method therefor A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals ... 03/23/06 - 20060063343 - Method for making thin film transistors with lightly doped regions A method for making a thin film transistor (TFT) with a lightly doped region. The process of the invention is compatible with the currently common TFT manufacturing processes. A substrate with a photoresist layer thereon is subjected to two-step exposure with different exposure energies to form a full-through pattern and ... 03/23/06 - 20060063342 - Method for manufacturing semiconductor device There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this ... 03/02/06 - 20060046414 - Method for producing a thermoelement A method for producing a thermoelement, in which a first and a second undoped thermoleg are generated on the surface of a substrate, a first resist mask is applied in such a way that the first thermoleg is not covered by it and the second thermoleg is covered by it, ... 01/19/06 - 20060014354 - Method of making transistor with strained source/drain A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially ... 12/08/05 - 20050272215 - Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two ... 09/29/05 - 20050215022 - Tri-gate low power device and method for manufacturing the same The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric ... 08/04/05 - 20050170597 - Semiconductor apparatus and method of manufacturing the same A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, ... 06/30/05 - 20050142792 - Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of ... 06/30/05 - 20050142791 - Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of ... 06/09/05 - 20050124130 - Semiconductor fabrication process with asymmetrical conductive spacers A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed ... ### FreshPatents.com Support |