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Semiconductor Device Manufacturing: Process > Forming Bipolar Transistor By Formation Or Alteration Of Semiconductive Active Regions Forming Bipolar Transistor By Formation Or Alteration Of Semiconductive Active RegionsForming Bipolar Transistor By Formation Or Alteration Of Semiconductive Active Regions patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/29/07 - 20070072383 - Phosphorus activated nmos using sic process A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure ... 03/01/07 - 20070048955 - Method for enhancing electrode surface area in dram cell capacitors Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, ... 02/15/07 - 20070037355 - Esd protection device for high voltage An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically ... 01/04/07 - 20070004161 - Bipolar transistor with high dynamic performances A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy. ... 01/04/07 - 20070004160 - Tunable semiconductor diodes A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode ... 12/14/06 - 20060281275 - Heterojunction bipolar transistor and manufacturing method thereof In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, ... 12/14/06 - 20060281274 - Nonvolatile resistive memory element A nonvolatile memory element includes a first material region, a second material and an oxidation material region including an oxidation material as a memory material region. The oxidation material includes an oxidized form of the first material and/or an oxidized form of the second material. The first material is selected ... 11/23/06 - 20060263993 - Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for soi bicmos with reduced buried oxide thickness for low-substrate bias operation The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at ... 11/09/06 - 20060252215 - Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for ... 11/09/06 - 20060252214 - Bipolar transistor and fabricating method thereof There is provided a bipolar transistor (with a respective fabrication method) that provides superior noise characteristics and gain diffusion. The fabricating method includes forming a first base region at a collector region, which in turn is formed on a substrate. A first silicon layer is formed on the base region, ... 10/05/06 - 20060223273 - Surface treatment in preparation for contact placement A contact is formed on indium-phosphide material. Regions of the indium-phosphide material are exposed. An energetic bombardment is performed on exposed regions of the indium-phosphide material. Metal is deposited on the exposed regions of the indium-phosphide material where energetic bombardment occurred. ... 09/07/06 - 20060199348 - Method for the integration of two bipolar transistors in a semiconductor body, semiconductor arrangement in a semiconductor body, and cascode circuit A method for the integration of two bipolar transistors in a semiconductor body, wherein, for the first bipolar transistor, a first emitter semiconductor region, a first base semiconductor region, and a first collector semiconductor region are produced. A recombination layer is applied to the first bipolar transistor, which is adjacent ... 09/07/06 - 20060199347 - Structure of a bipolar junction transistor and fabricating method thereof A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portions of the doped area. ... 08/31/06 - 20060194400 - Method for fabricating a semiconductor device A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers ... 08/24/06 - 20060189088 - Semiconductor device having a merged region and method of fabrication A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one ... 08/10/06 - 20060177986 - High ft and fmax bipolar transistor and method of making same A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion ... 04/27/06 - 20060088970 - Apparatus and method for the low-contamination, automatic crushing of silicon fragments A crusher for producing fine silicon fragments for semiconductor or solar applications from silicon fragments suitable for semiconductor or solar applications, comprises a plurality of crushing tools, the crushing tools having a surface made from a hard, wear-resistant material, wherein the crusher has a comminution ratio e of from 1.5 ... 03/02/06 - 20060046409 - Semiconductor device and method of producing the same A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor. ... 03/02/06 - 20060046408 - Semiconductor integrated device A semiconductor integrated apparatus, comprising: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p type of first well diffusion region formed along ... 01/26/06 - 20060019458 - Creating increased mobility in a bipolar device The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by ... 01/19/06 - 20060014353 - Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon ... 01/12/06 - 20060009002 - Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the ... 12/29/05 - 20050287754 - Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric ... 12/08/05 - 20050272214 - Electrophoretic assembly of electrochemical devices Methods are provided for making bipolar electrochemical devices, such as batteries, using electrophoresis. A bipolar device is assembled by applying a field that creates a physical separation between two active electrode materials, without requiring insertion of a discrete separator film or electrolyte layer. ... 11/10/05 - 20050250289 - Control of dopant diffusion from buried layers in bipolar integrated circuits An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the ... 10/20/05 - 20050233534 - Silicon germanium heterojunction bipolar transistor with carbon incorporation A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, ... 10/06/05 - 20050221570 - Process for producing a base connection of a bipolar transistor A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material ... 09/29/05 - 20050215020 - Component for electromagnetic waves and a method for manufacturing the same The present invention relates to a method for fabricating a cavity in substrate for a component for electromagnetic waves, the method comprising providing said cavity by removal of material from said substrate by removal of material by immersing the substrate in a liquid bath of a chemical etchant, so that ... 09/08/05 - 20050196930 - Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a region of a substrate of ... 08/18/05 - 20050181568 - Cmos imager with enhanced transfer of charge and low voltage operation and method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a complete charge transfer between the charge collection region ... 07/28/05 - 20050164463 - Multi-stage epi process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting substrate, forming a second layer of epitaxial silicon above the first ... 06/30/05 - 20050142787 - Method of fabricating self-aligned bipolar transistor The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includes the steps of forming a well in a substrate isolated ... ### FreshPatents.com Support |