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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Self-aligned > Source Or Drain Doping > Utilizing Gate Sidewall Structure > Plural Doping Steps Plural Doping StepsPlural Doping Steps patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/29/07 - 20070072382 - Method of manufacturing semiconductor device It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate ... 03/15/07 - 20070059894 - Selective deposition of germanium spacers on nitride A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride ... 03/08/07 - 20070054458 - Method of fabricating spacers and cleaning method of post-etching and semiconductor device A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substrate to cover the substrate and the device structure. ... 03/01/07 - 20070048953 - Graded dielectric layers Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, ... 01/11/07 - 20070010062 - Method to obtain fully silicided poly gate The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate electrodes 150 that are, in turn, located over a microelectronics substrate 110. The gate electrodes 150 have a doped region 170a located between them. A portion ... 01/04/07 - 20070004159 - Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation for formation of source/drain regions, on the entire surface of the semiconductor substrate ... 12/21/06 - 20060286758 - Super anneal for process induced strain modulation A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so ... 12/21/06 - 20060286757 - Semiconductor product and method for forming a semiconductor product The invention provides a semiconductor product (25) and a method for forming the semiconductor product (25), the semiconductor product (25) comprising a transistor (1) having first (11) and second source/drain regions (12) being arranged at bottom surfaces (B) of recesses (R) in a substrate (2). Due to the depth (d) ... 12/14/06 - 20060281273 - Semiconductor device and manufacturing method of the semiconductor device A semiconductor device includes a gate electrode disposed on a semiconductor layer via a gate insulating film; a source layer formed in the semiconductor layer to be separated by a first offset length from one end of said gate electrode; a drain layer formed in the semiconductor layer to be ... 10/26/06 - 20060240632 - Semiconductor device including air gap between semiconductor substrate and l-shaped spacer and method of fabricating the same A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and ... 09/07/06 - 20060199346 - Source/drain extensions having highly activated and extremely abrupt junctions A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. ... 09/07/06 - 20060199345 - Method for manufacturing field effect transistor The manufacturing stability can be improved while effectively inhibiting the short-channel effect in the transistor according to the present invention. A halo impurity having a conductivity type opposite to a first conductivity type of a first impurity is ion-implanted into the silicon substrate 101, and thereafter the first impurity having ... 08/31/06 - 20060194399 - Silicide gate transistors and method of manufacture A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried ... 08/31/06 - 20060194398 - Semiconductor device and its manufacturing method A semiconductor device which has a source/drain extension structure suitable for miniaturization, is provided a semiconductor device comprising a gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulator, a semiconductor region of a second conductivity type comprising first and second semiconductor areas, wherein ... 07/13/06 - 20060154429 - Method for fabricating low-defect-density changed orientation si The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention ... 06/22/06 - 20060134874 - Manufacture method of mos semiconductor device having extension and pocket A gate insulating film is formed on the surface of a semiconductor substrate in an opening of a field insulating film, and thereafter a gate electrode and a capacitor lower electrode made of doped polysilicon or the like are formed on the insulating film. Pocket regions are formed by an ... 06/15/06 - 20060128106 - Transistor and method for manufacturing thereof A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing ... 05/04/06 - 20060094196 - Method of fabricating semiconductor device, and semiconductor device Disclosed is a method of fabricating a semiconductor device that includes field effect transistors each having a gate electrode formed only of a metal suicide which overcomes the problem of depletion of the gate and makes adjustment of a work function easier, and that has a high integration with the ... 04/27/06 - 20060088969 - Solid phase epitaxy recrystallization by laser annealing Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor products. One method (70) includes a preamorphizing process (74) of ... 03/30/06 - 20060068556 - Semiconductor device and method for fabricating the same The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. ... 03/16/06 - 20060057811 - Selective post-doping of gate structures by means of selective oxide growth A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited ... 02/23/06 - 20060040452 - Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming ... 02/23/06 - 20060040451 - Method of forming an integrated circuit employable with a power converter A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a power switch of a power train of the power converter on a semiconductor substrate, and forming a driver switch of a driver configured to provide ... 02/23/06 - 20060040450 - Source/drain structure for high performance sub 0.1 micron transistors An asymmetric transistor structure comprising a gate structure with a drain halo ion implantation region, without any halo ion implantation region source region is provided. Methods of forming a transistor structure are also provided. An angled halo ion implant is preformed at an angle using ions of the same type ... 01/26/06 - 20060019457 - Methods of forming a transistor with an integrated metal silicide gate electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the ... 01/19/06 - 20060014352 - Method and apparatus providing cmos imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions ... 01/19/06 - 20060014351 - Low leakage mos transistor A method of forming a low leakage MOS transistor. The transistor includes a gate on a substrate with at least two first spacers adjacent to the gate. A first doped region is formed under each first spacer and a second doped region is formed adjacent to each first doped region, ... 01/12/06 - 20060009001 - A recessed polysilicon gate structure for a strained silicon mosfet device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the ... 11/24/05 - 20050260819 - Reduced dielectric constant spacer materials integration for high speed logic gates An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant ... 11/17/05 - 20050255660 - Ion implantation method for forming a shallow junction A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implantation method for forming a shallow junction comprises providing a ... 10/27/05 - 20050239258 - Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the ... 10/13/05 - 20050227447 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the ... 10/13/05 - 20050227446 - Sidewall spacer for semiconductor device and fabrication method thereof An offset spacer layer for an LDD ion implantation process is formed by blanket deposition without photolithography and dry etch processes. The offset spacer layer remaining on LDD regions during an ion implantation process prevents a substrate from silicon loss and dosage contamination and has densified characteristics to improve device ... 09/01/05 - 20050191817 - Semiconductor device and method of fabricating the same According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a gate electrode formed on the substrate via a gate insulating film and containing silicon, an insulating offset spacer formed on a side surface of the gate electrode and having an upper surface ... 09/01/05 - 20050191816 - Implanting carbon to form p-type source drain extensions The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments. ... 08/25/05 - 20050186748 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device including a plurality of MIS transistors formed on a semiconductor substrate, includes forming a plurality of gate electrodes associated with the MIS transistors on the semiconductor substrate, with a plurality of gate insulating films interposed between the gate electrodes and the semiconductor substrate, ... 08/04/05 - 20050170596 - Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are disclosed. A pattern of a polysilicon layer for a gate electrode and another pattern of a polysilicon layer for a resistor are respectively formed on an active region of a salicide region and a device isolation film of a ... 07/28/05 - 20050164461 - Method for forming a junction region of a semiconductor device A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed ... 06/30/05 - 20050142785 - Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a transistor channel area. The method includes forming a gate insulating layer on a semiconductor substrate, forming a channel ion area ... 06/23/05 - 20050136607 - Methods of fabricating semiconductor devices Methods of fabricating a semiconductor devices are disclosed. One example method includes forming a gate insulating layer and a gate electrode on a semiconductor substrate; forming first halo implant regions under the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming low concentration impurity regions for ... 06/23/05 - 20050136606 - Spacer for a gate electrode having tensile stress and a method of forming the same By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer ... 06/16/05 - 20050130381 - Methods for fabricating semiconductor devices Methods for stabilizing a threshold voltage in an NMOS transistor are disclosed. A disclosed method comprises: forming a gate electrode on an active region in a substrate of a first conductive type; implanting ions of a second conductive type into the active region to form LDD regions; forming spacers on ... 06/09/05 - 20050124128 - Methods for manufacturing semiconductor device Methods of forming a silicide layer with small grain boundary size on a source/drain region of semiconductor device are disclosed. A disclosed method comprises forming a gate insulating layer and a gate electrode on an active region of a semiconductor substrate; forming spacers on the sidewalls of the gate electrode; ... 06/02/05 - 20050118770 - Method for introducing hydrogen into a channel region of a metal oxide semiconductor (mos) device The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (230) over a substrate (210) and forming at least a portion of source/drain ... ### FreshPatents.com Support |