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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Self-aligned > Source Or Drain Doping > Utilizing Gate Sidewall Structure Utilizing Gate Sidewall StructureUtilizing Gate Sidewall Structure patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077717 - Method for forming transistor of semiconductor device A method for forming a transistor of a semiconductor device includes forming a spacer oxide film having a uniform thickness i at a high speed. The method includes forming a plurality of gate stacks on a semiconductor substrate; and forming a spacer oxide film on a plurality of the gate ... 03/29/07 - 20070072381 - Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of sin, sicn or siocn The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, ... 03/29/07 - 20070072380 - Methods for fabrication of a stressed mos device Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is ... 02/15/07 - 20070037354 - Semiconductor device having a structure to improve contact processing margin, and method of fabricating the same A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern ... 02/08/07 - 20070032028 - Structure and method for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations ... 01/25/07 - 20070020868 - Semiconductor processing method and field effect transistor A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with ... 01/18/07 - 20070015334 - Method for forming a fully silicided gate and devices obtained thereof A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume ... 01/04/07 - 20070004158 - Transistor having a germanium implant region located therein and a method of manufacture therefor The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of ... 12/14/06 - 20060281272 - Method and apparatus for increase strain effect in a transistor channel Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of ... 12/14/06 - 20060281271 - Method of forming a semiconductor device having an epitaxial layer and device thereof Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling silicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent ... 12/14/06 - 20060281270 - Raised source and drain process with disposable spacers A method for forming raised source and drain regions in a semiconductor manufacturing process employs double disposable spacers. A deposited oxide is provided between the first and second disposable spacers, and serves to protect the gate electrode, first disposable spacers and a cap layer during the dry etching of the ... 11/02/06 - 20060246673 - Semiconductor device comprising extensions produced from material with a low melting point A semiconductor device comprises a gate electrode (1) and a gate insulating layer (2) both surrounded by a spacer (3) and produced on a surface (S) of a substrate (100) of a first semiconductor material. The device also comprises a source region (4) and a drain region (5) both situated ... 09/14/06 - 20060205169 - Method for manufacturing a semiconductor device using a sidewall spacer etchback The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing ... 08/03/06 - 20060172502 - Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device ... 06/29/06 - 20060141728 - Formation of junctions and silicides with reduced thermal budget Method of formation of a metal-silicide layer (12, 13, 14, 18, 19) an a semiconductor substrate (1), the semiconductor substrate (1) including at least a dopant region (5); the dopant region (5) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process ... 05/11/06 - 20060099766 - Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion ... 04/06/06 - 20060073666 - Non-volatile memory device with conductive sidewall spacer and method for fabricating the same The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed ... 04/06/06 - 20060073665 - Source/drain extensions having highly activated and extremely abrupt junctions A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. ... 03/30/06 - 20060068555 - Structure and method for manufacturing mosfet with super-steep retrograded island The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure ... 02/23/06 - 20060040449 - Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by ... 02/09/06 - 20060030112 - Manufacturing methods and structures of memory device Dual spacer structures are fabricated such that sidewall spacers in a cell region are thinner than sidewall spacers in a periphery region. The fabricating method of memory includes forming a stop layer over the first semiconductor feature and the second semiconductor feature in cell region and periphery region. A spacer ... 02/02/06 - 20060024898 - Increased drive current by isotropic recess etch A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body ... 01/26/06 - 20060019456 - Transistor fabrication methods using dual sidewall spacers Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after ... 01/26/06 - 20060019455 - Transistor fabrication methods using reduced width sidewall spacers Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material ... 12/29/05 - 20050287752 - Methods for forming a transistor Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate ... 12/29/05 - 20050287751 - Multi-layer reducible sidewall process The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside ... 12/22/05 - 20050282346 - Mim capacitors A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned ... 12/08/05 - 20050272213 - Method of manufacturing metal-oxide-semiconductor transistor A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed ... 12/01/05 - 20050266649 - Electronic device manufacturing apparatus An electronic device manufacturing apparatus is provided with a support which includes a shelf for supporting a substrate, a sensor which obtains the position of the substrate and a position correcting mechanism which corrects the position of the substrate. Or alternatively, an electronic device manufacturing apparatus is provided with a ... 10/06/05 - 20050221568 - Manufacturing method of semiconductor device, semiconductor device, substrate for electro-optical device, electro-optical device, and electronic apparatus To provide a manufacturing method of a semiconductor device, which can form an LDD (lightly doped drain) structure in a self alignment manner, can suppress the length of a doped region, and can prevent characteristics from being unstabilized when oversaturated hydrogen atoms are implanted, a semiconductor device, a substrate for ... 09/29/05 - 20050215019 - Method of manufacturing metal-oxide-semiconductor transistor A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer ... 09/22/05 - 20050208726 - Spacer approach for cmos devices A semiconductor device having a graded source/drain region for use in CMOS devices is provided. The semiconductor device is formed by utilizing a spacer and a sacrificial spacer as masks. The sacrificial spacer is formed over an etch stop layer, which acts as an etch stop and protects underlying structures ... 09/15/05 - 20050202643 - Transistor and method for manufacturing the same A transistor and a method for manufacturing the same are disclosed. One cell transistor having SIS (silicon-insulator-silicon) structure and two cell transistors having SONOS (silicon-oxide-nitride-oxide-silicon) structure constitute the transistor of the present invention which can store 2 bits. The cell transistor having SIS structure and the cell transistors having SONOS ... 09/01/05 - 20050191815 - Metal-oxide-semiconductor device including a buried lightly-doped drain region An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed ... 07/28/05 - 20050164459 - Soft-landing etching method using doping level control The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with ... 07/21/05 - 20050158959 - Quantum wire gate device and method of making same The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride ... 06/30/05 - 20050142784 - Methods of fabricating semiconductor devices Methods of fabricating semiconductor devices are disclosed wherein void generation in an insulating interlayer between a pair of gate electrodes is prevented. An illustrated method includes: forming a gate on a semiconductor substrate, forming lightly doped regions in the substrate, forming spacers on sidewalls of the gate with liners disposed ... 06/30/05 - 20050142783 - Methods of fabricating gate spacers for semiconductor devices A method of fabricating the gate spacers of semiconductor devices is disclosed. An example method forms a gate on a semiconductor substrate, deposits a buffer oxide layer and a nitride layer sequentially on the whole semiconductor substrate including the gate, and forms spacers by etching the nitride layer. ... 06/30/05 - 20050142782 - Methods of manufacturing a mos transistor Methods of manufacturing MOS transistors which are capable of suppressing a short channel effect are disclosed. The short channel effect is suppressed by forming source/drain regions of a shallow junction and sufficiently doping a gate. An illustrated method includes: forming a gate insulating layer and a gate on a semiconductor ... 06/30/05 - 20050142781 - Semiconductor device having an etch stopper formed of a sin layer by low temperature ald and method of fabricating the same Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride ... 06/23/05 - 20050136605 - Mos transistor gates with thin lower metal silicide and methods for making the same Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by ... 06/16/05 - 20050130380 - Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level A semiconductor device includes a metal silicide interconnect structure and a dielectric layer that are located at substantially the same fabrication level. The metal silicide interconnect and dielectric layer may be fabricated by forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming ... 06/09/05 - 20050124127 - Method for manufacturing gate structure for use in semiconductor device The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal ... 06/09/05 - 20050124126 - Method for fabricating silicide A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the ... 06/02/05 - 20050118769 - Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, ... ### FreshPatents.com Support |