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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Self-aligned > Source Or Drain Doping Source Or Drain DopingSource Or Drain Doping patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082451 - Methods to fabricate mosfet devices using a selective deposition process In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing ... 04/12/07 - 20070082450 - Semiconductor device and method of manufacturing such a semiconductor device The invention relates to a semiconductor device (10) with a substrate and a semiconductor body (1) comprising a first FET (3) with a source (2) and a drain (3) that are provided with connection regions (2B, 3B) of a metal silicide, and that are connected to source and drain extensions ... 03/22/07 - 20070066024 - Phosphorus activated nmos using sic process A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure ... 03/01/07 - 20070048952 - Method to manufacture ldmos transistors with improved threshold voltage control A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant ... 03/01/07 - 20070048951 - Method for production of semiconductor memory devices Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. ... 02/08/07 - 20070032026 - Formation of strained si channel and si1-xgex source/drain structures using laser annealing A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal ... 02/01/07 - 20070026618 - Method of manufacturing high-voltage device A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can be secured. ... 01/25/07 - 20070020867 - Buried stress isolation for high-performance cmos technology A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises ... 01/25/07 - 20070020866 - Cmos transistor with high drive current and low sheet resistance A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain region substantially aligned with an edge of ... 01/25/07 - 20070020865 - Multi-work function gates for cmos circuit and method of manufacture A method of manufacturing a device and the device. The device includes doping a low voltage threshold area and a high voltage threshold area. The method further includes forming gate structures over the low voltage threshold area and the high voltage threshold area and protecting the gate structure over the ... 12/28/06 - 20060292807 - Semiconductor device and method of fabricating the same A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate electrode region; a first conductive layer formed on ... 12/14/06 - 20060281269 - Method and structure of an auxiliary transistor arrangement used for fabricating a semiconductor memory device Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone. ... 12/14/06 - 20060281268 - Short channel semiconductor device fabrication The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region and/or source/drain regions to mitigate the establishment of ... 12/14/06 - 20060281267 - Method for improving threshold voltage stability of a mos device This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on a semiconductor substrate. A gate dielectric layer is formed on the well of the semiconductor substrate. A gate conductive layer ... 11/30/06 - 20060270172 - Method for changing threshold voltage of device in resist asher A method for forming a dopant in a substrate, by accumulating at least one dopant species in an asher chamber and forming the accumulated dopant species on an exposed portion of the substrate. A target concentration for the plasma chamber dopant species is determined by test or measurement. The asher ... 11/23/06 - 20060263992 - Method of forming the n-mos and p-mos gates of a cmos semiconductor device A method for forming the N-MOS and P-MOS transistor regions of a CMOS device having reduced depletion of the N and P dopants in the polysilicon gate and reduced penetration of the N and P dopants through the oxide layer and into the channel regions of the N-MOS and the ... 11/16/06 - 20060258109 - Dram cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the ... 11/16/06 - 20060258108 - Semiconductor memory In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer has a protrusion portion and a depressed portion on a cross section taken along a plane that includes ... 11/09/06 - 20060252213 - Silicide process utilizing pre-amorphization implant and second spacer A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain are implanted into the substrate. A second ... 11/09/06 - 20060252212 - Method and device Method for producing a field effect transistor having a source region (9), a drain region and a channel layer (11) interconnecting the source and drain regions, and including the step of providing a sacrificial layer (4) on part of a semiconductor material (1) whose edge is used to define the ... 11/02/06 - 20060246672 - Method of forming a locally strained transistor A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, ... 10/26/06 - 20060240630 - Methods of making substitutionally carbon-doped crystalline si-containing materials by chemical vapor deposition Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may ... 09/28/06 - 20060216899 - Silicide process utilizing pre-amorphization implant and second spacer A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain are implanted into the substrate. A second ... 07/27/06 - 20060166449 - Nonvolatile memory device for storing multi-bit data A semiconductor nonvolatile memory device for storing multi-bit data has a memory cell having a source region S and a drain region D formed at the surface of a semiconductor substrate, a gate insulator film and a control gate CG formed on a channel region CH between the source region ... 07/13/06 - 20060154427 - Method of thermally treating a wafer and method of fabricating a semiconductor device using the same A method of thermally treating a semiconductor wafer is disclosed. The method comprises loading a wafer into a chamber, adjusting the vacuum pressure in the chamber, increasing the temperature of the wafer, and maintaining the vacuum pressure and temperature for a period of time sufficient to activate conductive impurities that ... 07/06/06 - 20060148184 - Method for forming ldmos channel A method of forming an LDMOS channel is provided. The method includes forming a conductive epitaxial layer on a semiconductor substrate, forming a photoresist pattern, implanting P-type and N-type ions with a first level of energy by using a tilt implantation method onto the semiconductor substrate, and implanting P-type ions ... 06/29/06 - 20060141726 - Field effect transistor with a high breakdown voltage and method of manufacturing the same An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer ... 06/29/06 - 20060141725 - Method of manufacturing flash memory device A method of manufacturing a flash memory device wherein before an insulating film spacer of a contact region is removed after a gate line and source/drain are formed, a high quality buffer oxide film formed between the gate line and the insulating film spacer is made dense by means of ... 06/29/06 - 20060141724 - Method of manufacturing mos transistor A method of manufacturing a MOS transistor capable of suppressing a short channel effect by suppressing boron (B) ion diffusion in the MOS transistor. The method includes steps of: forming an impurity diffusion suppressing layer in an active region of a semiconductor substrate; forming an impurity layer containing boron ions ... 06/22/06 - 20060134873 - Tailoring channel strain profile by recessed material composition control The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are formed (106) in active regions of a semiconductor device after formation of gate structures according ... 06/08/06 - 20060121680 - Semiconductor device and manufacturing method thereof It is an object of the present invention to provide a semiconductor device superior in the decrease in leak current due to a short-channel effect and a manufacturing method thereof. In a process of forming a field-effect transistor over a single-crystal semiconductor substrate, an impurity is introduced to form an ... 05/18/06 - 20060105531 - Method of forming notched gate structure A method of forming a notched gate structure comprising a semiconductor substrate having a first oxide layer formed thereon. A first conductive layer is formed on the semiconductor substrate. A portion of the first conductive layer and a portion of the first oxide layer are removed to form first gate ... 05/11/06 - 20060099765 - Method to enhance cmos transistor performance by inducing strain in the gate and channel A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate. The method forms an optional oxide layer on the NMOS transistors and the ... 05/11/06 - 20060099764 - Method of fabricating a lateral double-diffused mosfet (ldmos) transistor A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow. ... 05/04/06 - 20060094195 - Method of manufacturing semiconductor mos transistor device A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. ... 05/04/06 - 20060094194 - Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90nm cmos technology A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy ... 04/13/06 - 20060079061 - Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in ... 04/06/06 - 20060073664 - Semiconductor device and manufacturing method of the same Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted ... 03/02/06 - 20060046407 - Dram cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the ... 03/02/06 - 20060046406 - Programming, erasing, and reading structure for an nvm cell A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being ... 02/02/06 - 20060024897 - Method of manufacturing lateral mosfet structure of an integrated circuit having separated device regions Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the ... 12/29/05 - 20050287750 - Transistor, method of fabricating the same, and light emitting display comprising the same A light emitting display comprises: at least one first metal layer; a second metal layer crossing the first metal layer and having a first width; a light emitting device formed adjacent to a region where the first metal layer and the second metal layer cross each other; and a pixel ... 12/22/05 - 20050282345 - Transistor with vertical dielectric structure A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure ... 12/08/05 - 20050272212 - Method of high precision printing for manufacturing organic thin film transistor A method of high precision printing for manufacturing organic thin film transistor, comprising the following steps of: forming a gate on a substrate; forming an insulator layer on the substrate; forming a conducting wire electrode film on the insulator layer; forming a organic interlayer; forming a organic semiconductor layer on ... 10/20/05 - 20050233532 - Method of forming sidewall spacers The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant ... 10/06/05 - 20050221567 - High performance, integrated, mos-type semiconductor device and related manufacturing process An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material ... 09/29/05 - 20050215017 - Method for reducing a short channel effect for nmos devices in soi circuits Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or ... 09/15/05 - 20050202642 - Method of forming polysilicon gate structures with specific edge profiles for optimization of ldd offset spacing Methods of forming MOSFET devices featuring LDD regions offset from the edges of conductive gate structures has been developed. A first embodiment of this invention features the definition of a tapered conductive gate structure with the foot of the tapered structure larger in width than the top of the structure. ... 09/01/05 - 20050191813 - Asymmetric source/drain transistor employing selective epitaxial growth (seg) layer and method of fabricating same According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate ... 08/25/05 - 20050186747 - Cmos silicide metal gate integration The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, ... 08/18/05 - 20050181566 - Method for doping impurities, methods for producing semiconductor device and applied electronic apparatus A solution containing impurity ions is applied onto the surface of a silicon film to form a solution layer, followed by drying into a compound layer containing the impurities. Heat treatment is performed by irradiation with an energy beam so as to diffuse the impurity atoms in the compound layer ... 08/04/05 - 20050170595 - Semiconductor device layout and channeling implant process A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the ... 06/23/05 - 20050136604 - Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into ... 06/09/05 - 20050124125 - Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors A method for forming a transistor includes forming a gate dielectric layer over a portion of a semiconductor substrate, the substrate being substantially free of silicon; defining a gate electrode over a portion of the gate dielectric layer; and introducing ions into the substrate proximate the gate electrode to define ... 06/02/05 - 20050118768 - Method of forming high voltage metal oxide semiconductor transistor A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate structure is formed by using the first patterned photoresist layer as a hard mask. A second patterned photoresist layer is ... ### FreshPatents.com Support |