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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Self-aligned > Having Elevated Source Or Drain (e.g., Epitaxially Formed Source Or Drain, Etc.) Having Elevated Source Or Drain (e.g., Epitaxially Formed Source Or Drain, Etc.)Having Elevated Source Or Drain (e.g., Epitaxially Formed Source Or Drain, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077716 - Method and structure for second spacer formation for strained silicon mos transistors A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form ... 03/22/07 - 20070066023 - Method to form a device on a soi substrate A method and apparatus for depositing a planar silicon containing layer, depositing an oxide layer, patterning the oxide layer to expose regions of the silicon containing layer above remaining regions of the oxide layer, selectively depositing a silicon and germanium containing layer on the regions of the silicon containing layer, ... 03/15/07 - 20070059892 - Method for fabricating a semiconductor structure A semiconductor structure is fabricated to have a transistor cell region and a connection region. The transistors both of a transistor cell region and of a connection region are coated with a first oxide layer, the layer thickness of the first oxide layer being dimensioned in such a way that ... 03/01/07 - 20070048950 - Magnetic devices and techniques for formation thereof Techniques for forming a magnetic device are provided. In one aspect, a method of forming a via hole self-aligned with a magnetic device comprises the following steps. A dielectric layer is formed over at least a portion of the magnetic device. The dielectric layer is configured to have an underlayer ... 02/08/07 - 20070032025 - Method for forming germanides and devices obtained thereof The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited ... 02/01/07 - 20070026617 - Method of fabricating semiconductor side wall fin A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance. ... 01/25/07 - 20070020864 - Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers ... 12/07/06 - 20060275993 - Low ohmic layout technique for mos transistors A method of making a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the ... 12/07/06 - 20060275992 - Method to improve drive current by increasing the effective area of an electrode The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the ... 10/26/06 - 20060240629 - Self correcting suppression of threshold voltage variation in fully depleted transistors A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second ... 10/12/06 - 20060228863 - Method for making a semiconductor device with strain enhancement A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode ... 09/14/06 - 20060205168 - Method of fabricating a lateral double-diffused mosfet (ldmos) transistor A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed. ... 09/14/06 - 20060205167 - Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A ... 08/17/06 - 20060183290 - Manufacturing method for semiconductor device and rapid thermal annealing apparatus During a manufacturing process for a semiconductor device, the size of gate electrodes is measured within the wafer surface. The gained measurement data is compared with the data which depends on the gate length-electrical properties of the semiconductor elements, and thus, distribution in the electrical properties within the wafer surface ... 08/03/06 - 20060172501 - Method of manufacturing semiconductor device Provided is a method of manufacturing a high-quality silicon epitaxial growth. (SEG) layer on a highly doped silicon substrate. The method includes providing a semiconductor substrate including dopant areas with a predetermined concentration, implanting group IV ions into the substrate, cleaning the substrate using a chlorine-based gas, and forming a ... 08/03/06 - 20060172500 - Stucture and method to induce strain in a semiconductor device channel with stressed film under the gate A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply ... 08/03/06 - 20060172499 - Structure and method for thin box soi device A method of forming a semiconductor device, comprising providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of ... 07/13/06 - 20060154426 - Finfets with long gate length at high density A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the ... 06/29/06 - 20060141723 - Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor ... 06/22/06 - 20060134872 - Strained nmos transistor featuring deep carbon doped regions and raised donor doped source and drain Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels. ... 06/15/06 - 20060128105 - High mobility heterojunction complementary field effect transistors and methods thereof A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the ... 06/08/06 - 20060121679 - Semiconductor device and method for manufacturing the same The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another ... 06/01/06 - 20060115949 - Semiconductor fabrication process including source/drain recessing and filling A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially ... 04/20/06 - 20060084235 - Low rc product transistors in soi semiconductor process A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. ... 04/13/06 - 20060079060 - Semiconductor device having elevated source/drain and method of fabricating the same The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second ... 04/06/06 - 20060073663 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming a semiconductor region containing silicon and an insulator region on a major surface of a semiconductor substrate containing silicon as a main component; depositing a semiconductor film containing silicon as a main component on the semiconductor region and the insulator region; ... 03/16/06 - 20060057810 - Surface preparation method for selective and non-selective epitaxial growth According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of ... 02/02/06 - 20060024896 - Method for fabricating metal-oxide-semiconductor transistor with selective epitaxial growth film A method for forming MOS transistor with improved resistance to HF attack during a pre-SEG clean process is disclosed. The MOS transistor encompasses a substrate having a gate with sidewalls. The gate is patterned on the main surface of the substrate. Source/drain doping regions are formed on opposite sides of ... 01/12/06 - 20060009000 - Method of fabricating coil-embedded inductor A method of fabricating a coil-embedded inductor provides steps for obtaining uniform density of coil-embedded inductor. The cavity of a first die is filled with dust before being flipped, and then filled with dust a second time. The dust in the cavity is pressed only once for improving the density. ... 01/05/06 - 20060003534 - Salicide process using bi-metal layer and method of fabricating semiconductor device using the same A salicide process using a bi-metal layer and method of fabricating a semiconductor substrate using the same are disclosed herein. The salicide process includes forming a main metal layer on a semiconductor substrate containing silicon. A main metal alloy layer containing at least one species of alloy element is formed ... 01/05/06 - 20060003533 - Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer ... 12/22/05 - 20050282344 - Mosfet and method of fabricating the same A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating ... 12/15/05 - 20050277259 - Manufacturing method of gate oxidation films After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist ... 12/15/05 - 20050277258 - Method for forming self-aligned contact in semiconductor device A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized ... 11/24/05 - 20050260818 - Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device includes:isolating a SOI layer on a buried oxide film with a pair of element isolation regions having a perpendicular sidewall; depositing a poly-crystal silicon layer on the isolated SOI layer; implanting a dopant into the poly-crystal silicon layer; depositing a silicon oxide film ... 11/10/05 - 20050250287 - Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing A semiconductor fabrication process includes forming a gate electrode overlying a substrate. A first silicon nitride spacer is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer is then formed adjacent the offset spacer. An elevated source/drain structure, defined by the boundaries of the disposable spacer, is ... 08/25/05 - 20050186746 - Method of manufacturing a fin field effect transistor In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of ... 08/11/05 - 20050176206 - Method and system for forming a contact in a thin-film device An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil depositing a dielectric material, planarizing the dielectric material thereby exposing ... 08/04/05 - 20050170594 - Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the ... 07/21/05 - 20050158958 - Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed ... 06/30/05 - 20050142780 - Method of fabricating a fin transistor A method of fabricating a fin transistor is disclosed. An example method stacks a mask oxide layer and a nitride layer on a semiconductor substrate, forms a fin by etching the nitride and mask oxide layers and silicon, forms an insulating oxide layer, and forms a gate electrode by etching ... 06/30/05 - 20050142779 - Semiconductor device having mos varactor and methods for fabricating the same In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A ... 06/30/05 - 20050142778 - Method for forming inductor in semiconductor device The present invention relates to a method for forming an inductor being a passive device in RE MEMS, RFCMOS, Bipolor/SiGe, BiCMOS semiconductor devices. According to the present method, a lower photoresist layer, an intermediate anti-exposure layer and an upper photoresist layer are sequentially formed on a substrate having a lower ... 06/09/05 - 20050124124 - Method for fabricating a semiconductor structure A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active ... 06/09/05 - 20050124123 - Fabrication method for semiconductor device and manufacturing apparatus for the same A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after ... ### FreshPatents.com Support |