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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Self-aligned Self-alignedSelf-aligned patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077715 - Semiconductor device and method of fabricating the same Example embodiments relate to a semiconductor device and a method of fabricating the same. A dummy pattern may be formed on a semiconductor substrate. Source and drain regions may be formed on the semiconductor substrate at sides of the dummy pattern. A first metal silicide layer may be formed on ... 03/15/07 - 20070059891 - Mandrel/trim alignment in sit processing Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, ... 03/08/07 - 20070054457 - Method of fabricating mos transistor having epitaxial region Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an ... 02/22/07 - 20070042556 - Method of fabricating metal oxide semiconductor transistor A method of fabricating a metal oxide semiconductor transistor is described. A substrate having device isolation structures thereon is provided. A stack gate structure is formed over the substrate. An etching stop layer is formed over the substrate to cover the stack gate structure, the substrate and the device isolation ... 02/08/07 - 20070032024 - Methods for fabricating a stressed mos device A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench ... 02/01/07 - 20070026616 - Method for fabricating semiconductor device and semiconductor device fabricated using the same Provided are a method for fabricating a semiconductor device and a semiconductor device fabricated using the same. The method for fabricating a semiconductor device comprises forming gate stacks on a semiconductor substrate, forming gate spacers made of a dielectric material having a dielectric constant of 2 to 4, on the ... 01/04/07 - 20070004157 - Method of fabricating a light emitting device There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manufacturing period thereof is shortened. A feature is that ... 01/04/07 - 20070004156 - Novel gate sidewall spacer and method of manufacture therefor The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, ... 12/28/06 - 20060292806 - Semiconductor integrated circuit device To improve a degree of integration and reliability of a semiconductor integrated circuit device. There are included third wire 14 arranged in the same layer as first wire 11 and second wire 12 and arranged in a direction intersecting with the first wire 11 and the second wire 12, first ... 12/21/06 - 20060286756 - Semiconductor process and method for reducing parasitic capacitance A semiconductor processes is described. A substrate having trench isolation structures and dummy trench isolation structures thereon is provided. Gate structures and dummy gate structures are simultaneously formed on the substrate. Spacers are formed on the sidewalls of the gate structures and the dummy gate structures. A patterned blocking layer ... 12/21/06 - 20060286755 - Method for fabricating transistor with thinned channel A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process. ... 12/14/06 - 20060281266 - Method and apparatus for adjusting feature size and position Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The critical dimension of the spacers is selected ... 11/16/06 - 20060258107 - Methods of forming field effect transistors and methods of forming field effect transistor gates and gate lines In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than ... 10/26/06 - 20060240628 - High voltage device and method for forming the same The invention is directed to a method for manufacturing a high voltage device. The method comprises steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in ... 09/14/06 - 20060205166 - Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device includes the steps of (a) forming a gate insulating film above a semiconductor substrate, (b) forming a first conductive film on the gate insulating film, (c) forming a first insulating film pattern on the first conductive film, (d) selectively forming a first impurity ... 09/07/06 - 20060199344 - Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device includes the steps of (a) forming a first region by selectively ion-implanting a second conductive type impurity into a first conductive type semiconductor layer without thermally diffusing an impurity, (b) forming a gate electrode including an edge vicinity region that is aligned with ... 08/24/06 - 20060189087 - Semiconductor device and method for fabricating the same A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing ... 07/20/06 - 20060160315 - Semiconductor device manufacturing method, wiring and semiconductor device In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a ... 07/06/06 - 20060148183 - Semiconductor device having high voltage mos transistor and fabrication method thereof A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an ... 06/29/06 - 20060141722 - Method of sequentially forming silicide layer and contact barrier in semiconductor integrated circuit device A method of sequentially forming a silicide layer and a contact barrier in a semiconductor device is provided. In the method, a pre-metal dielectric layer is deposited over an underlying structure that has a silicon substrate, a gate electrode on the substrate, and source/drain regions in the substrate. Contact holes ... 06/29/06 - 20060141721 - Semiconductor transistor device and method for manufacturing the same A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in ... 06/29/06 - 20060141720 - Method of fabricating mos transistor A method for fabricating a MOS transistor is suitable for modifying the configuration of a gate electrode. The method includes coating a first oxide layer on a semiconductor substrate and removing a predetermined width of the first oxide layer; forming an LDD region in the substrate; forming a gate spacer ... 06/29/06 - 20060141719 - Method of fabricating semiconductor device A gate is formed on a predetermined area of a substrate. A spacer insulating layer is formed on sidewalls of the gate. An insulating interlayer is formed over the substrate including the gate and the spacer insulating layer. Polymer generation is simultaneously carried out on a lateral side of the ... 06/01/06 - 20060115948 - Manufacturing method of semiconductor device Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited ... 05/11/06 - 20060099763 - Method of manufacturing semiconductor mos transistor device A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. ... 05/04/06 - 20060094193 - Semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS ... 04/27/06 - 20060088968 - Methods of fabricating a semiconductor device using a selective epitaxial growth technique Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an ... 04/20/06 - 20060084234 - Method for producing a spacer structure A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is ... 04/06/06 - 20060073662 - Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is ... 03/16/06 - 20060057809 - Methods for selective deposition to improve selectivity Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area ... 02/23/06 - 20060040448 - Method for fabricating a semiconductor device having improved hot carrier immunity ability The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive ... 02/16/06 - 20060035435 - Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed ... 02/02/06 - 20060024895 - Thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact on the semiconductor layer; forming a data ... 12/29/05 - 20050287749 - Methods for forming openings in doped silicon dioxide Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma processing chamber. An etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas ... 12/29/05 - 20050287748 - Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate ... 11/24/05 - 20050260817 - Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semiconductor device includes a semiconductor substrate; a gate insulating layer ... 11/17/05 - 20050255659 - Cmos transistor using high stress liner layer A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The second and third dielectric structures ... 09/01/05 - 20050191812 - Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to si, sige strained silicon schemes A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by ... 08/11/05 - 20050176205 - Method of forming a transistor using selective epitaxial growth A method of forming a transistor involves firstly forming at least one gate structure on a semiconductor substrate. Then, a surface cleaning process is performed. In the surface cleaning process, a chemical oxidation method is utilized for forming a first oxide layer on a surface of the semiconductor substrate not ... 07/28/05 - 20050164458 - Lightly doped drain mos transistor A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack comprising one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the ... 07/21/05 - 20050158957 - Creating shallow junction transistors A polysilicon structure may be defined on a semiconductor substrate using plasma doping to dope the sidewalls and upper surface of the polysilicon material as well as the source drain extensions. Shortly after plasma doping, the structure may be encapsulated within a suitable capping layer to prevent the removal of ... 07/07/05 - 20050148148 - Method of forming a source/drain and a transistor employing the same A method of forming a source/drain having a reduced junction capacitance and a transistor employing the same. In one embodiment, the method of forming the source/drain includes forming a recess in a substrate adjacent a gate of the transistor and forming a deep doped region below a bottom surface of ... 07/07/05 - 20050148147 - Amorphous etch stop for the anisotropic etching of substrates Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. ... 06/23/05 - 20050136603 - Manufacturing method of semiconductor device This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a ... 06/02/05 - 20050118767 - Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain regions. The superlattice may include a plurality ... ### FreshPatents.com Support - Terms & Conditions |