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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Including Isolation Structure > Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material Dielectric Isolation Formed By Grooving And Refilling With Dielectric MaterialDielectric Isolation Formed By Grooving And Refilling With Dielectric Material patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087510 - Semiconductor devices and manufacturing methods of the same A semiconductor device may include first and second silicon layers formed over a semiconductor substrate. An insulating layer may be formed between first and second silicon layers. A gate insulating layer, a gate electrode, and a spacer may be formed over a second silicon layer. A source/drain impurity area may ... 01/25/07 - 20070020862 - Semiconductor device and method of fabricating the same In an embodiment, a semiconductor device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate of the field region to define the active region, and has a protrusion higher than a ... 01/25/07 - 20070020861 - Method to engineer etch profiles in si substrate for advanced semiconductor devices Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material ... 11/30/06 - 20060270170 - Semiconductor device and method of manufacturing same A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, ... 11/23/06 - 20060263991 - Semiconductor device having shallow trench isolation structure and method of manufacturing the same In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper ... 11/23/06 - 20060263990 - Methods to form oxide-filled trenches A thermal oxidation process is used to fill trenches with an oxide; however, the oxidation process consumes some of the silicon. The embodiments herein advantageously apply this tendency for the oxidation process to consume silicon so as to convert all the silicon substrate material between the multiple trenches into an ... 10/05/06 - 20060223272 - Semiconductor device and method of manufacturing the same Each of channel regions 2a and 3b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structure ... 09/14/06 - 20060205165 - Polysilazane perhydride solution and method of manufacturing a semiconductor device using the same Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a ... 09/14/06 - 20060205164 - Method of forming a shallow trench isolation structure A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and ... 08/31/06 - 20060194397 - Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is ... 07/27/06 - 20060166448 - Apparatus for depositing seed layers One embodiment of the present invention is an apparatus for depositing seed layers over a substrate, said substrate includes at least one opening surrounded by a field, the apparatus includes: (a) a CVD chamber adapted to deposit a CVD seed layer over the substrate; (b) a PVD chamber adapted to ... 06/29/06 - 20060141717 - Method of forming isolation film in semiconductor device The present invention relates to a method of forming isolation films of a semiconductor device. According to the present invention, an oxidization process is performed to oxidize inner walls of trenches in a pre-heating period where temperature is raised in order to deposit an insulating material within a chamber so ... 05/25/06 - 20060110887 - Microelectronic device and a method for its manufacture Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of ... 04/27/06 - 20060088967 - Finfet transistor process The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the ... 04/20/06 - 20060084233 - Method for forming sti structures with controlled step height STI structures with step height control are produced using a relatively thin nitrogen-containing layer formed over a substrate. The nitrogen-containing layer may consist of SiN and SiON films with a combined thickness of 900 angstroms or less. Trench openings are formed to extend through the nitrogen-containing layer and into the ... 04/06/06 - 20060073661 - Method for forming wall oxide layer and isolation layer in flash memory device Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the trenches. This process prohibits formation of ... 03/30/06 - 20060068554 - Process for etching trenches in an integrated optical device The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas ... 03/23/06 - 20060063338 - Shallow trench isolation depth extension using oxygen implantation The present invention is directed to structures and fabrication methods used to construct an improved shallow trench isolation structure are disclosed. The method involves providing a semiconductor substrate having a shallow isolation trench. The trench is implanted with oxygen to form an implanted region at the bottom of the trench. ... 03/09/06 - 20060051926 - Methods of forming semiconductor devices having a trench with beveled corners A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench such that the oxide layer is ... 02/09/06 - 20060030111 - Method of manufacturing semiconductor device There has heretofore been a problem that desired withstanding characteristics cannot be obtained since a buried diffusion layer climbs up more than necessary in other heat treatment steps. In the present invention, after an N-type buried diffusion layer is formed, dry etching is performed in order to round off corner ... 02/09/06 - 20060030110 - Semiconductor memory device and method of manufacturing the same A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a semiconductor wafer, a trench ferroelectric capacitor formed in the ... 02/02/06 - 20060024894 - Capacitor in semiconductor device and method for fabricating the same The present invention relates to a capacitor in a semiconductor device and a method for fabricating the same. The capacitor fabrication method includes the steps of: forming a lower electrode by using a thin film of (Ba,Sr)RuO3 (BSR) on a substrate provided with various device elements; forming a dielectric layer ... 01/05/06 - 20060003532 - Semiconductor device and method of manufacturing therefor An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling ... 12/22/05 - 20050282343 - Method of forming transistor having channel region at sidewall of channel portion hole According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of ... 12/15/05 - 20050277257 - Gap filling with a composite layer A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a ... 12/08/05 - 20050272211 - Adjustable shims and washers A method comprising disposing an active device comprising a shape memory polymer upon a first surface; wherein the active device is operative to change at least one physical attribute in response to a thermal activation signal; activating the active device with a thermal activation signal to substantially decrease its modulus, ... 12/01/05 - 20050266648 - Methods of forming field effect transistors having recessed channel regions Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein ... 12/01/05 - 20050266647 - Method of manufacturing a semiconductor device Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of ... 12/01/05 - 20050266646 - Method of forming trench in semiconductor device There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of ... 10/27/05 - 20050239257 - Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a ... 10/06/05 - 20050221566 - Enhancing strained device performance by use of multi narrow section layout A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between ... 09/29/05 - 20050215016 - Method of fabricating a three-dimensional mosfet employing a hard mask spacer A method of fabricating a 3D field effect transistor employing a hard mask spacer includes forming a hard mask pattern on a semiconductor substrate. The semiconductor substrate is etched using the hard mask pattern as an etch mask to form a trench that defines an active region. A trench oxide ... 09/08/05 - 20050196929 - Low-thermal-budget gapfill process A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at ... 09/08/05 - 20050196928 - Method of reducing sti divot formation during semiconductor device fabrication STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to ... 09/01/05 - 20050191811 - Film forming ring and method of manufacturing semiconductor device There is here disclosed a film forming ring comprising a ring main body being made of an insulating material and formed in an annular shape along an edge of a substrate on which a film forming process by using a material gas in a plasma state is applied, and an ... 08/04/05 - 20050170593 - Method for forming a finfet by a damascene process A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as ... 07/07/05 - 20050148146 - High performance strained cmos devices A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a ... 06/30/05 - 20050142776 - Methods of fabricating semiconductor devices Methods of recovering damage on a semiconductor device by performing a hydrogen annealing process are disclosed. An example disclosed method includes forming an STI structure on a semiconductor substrate; forming a gate electrode and spacers on the sidewalls of the gate electrode; implanting ions into source and drain regions and ... 06/30/05 - 20050142775 - Method for isolating semiconductor devices A method of isolating semiconductor devices including forming a pad layer on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined depth using the pad layer as an etch barrier, implanting ion impurities into a bottom of the trench so as to increase an oxidation ... 06/30/05 - 20050142774 - Method for fabricating transistor of semiconductor device A method for fabricating a transistor of semiconductor is disclosed. A disclosed method comprises: forming an STI structure and a well region in a silicon substrate; forming a first dummy gate electrode including spacers and a first gate oxide layer on the well region; forming source and drain regions including ... 06/30/05 - 20050142773 - Structure and method for protecting substrate of an active area A structure and method are provided for protecting a substrate of an active area adjacent to an isolation region. A substrate including an isolation region is provided, wherein a gate is disposed on the substrate adjacent to the isolation region. A sacrificial protective layer is deposited on the substrate and ... 06/23/05 - 20050136602 - Dual-trench isolated crosspoint memory array A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the ... 06/23/05 - 20050136601 - Non-volatile semiconductor memory devices having self-aligned gate conductive layers and methods of fabricating such devices A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation patterns are formed on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate. The density of ... 06/23/05 - 20050136600 - Magnetic elements with ballistic magnetoresistance utilizing spin-transfer and an mram device using such magnetic elements A method and system for providing a magnetic element is disclosed. The method and system include providing a pinned layer, a magnetic current confined layer, and a free layer. The pinned layer is ferromagnetic and has a first pinned layer magnetization. The magnetic current confined layer has at least one ... 06/16/05 - 20050130378 - Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, ... ### FreshPatents.com Support |