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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Doping Of Semiconductive Channel Region Beneath Gate Insulator (e.g., Adjusting Threshold Voltage, Etc.) Doping Of Semiconductive Channel Region Beneath Gate Insulator (e.g., Adjusting Threshold Voltage, Etc.)Doping Of Semiconductive Channel Region Beneath Gate Insulator (e.g., Adjusting Threshold Voltage, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/08/07 - 20070054456 - Semiconductor device and method for fabricating the same A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage ... 11/30/06 - 20060270168 - End of range (eor) secondary defect engineering using chemical vapor deposition (cvd) substitutional carbon doping A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to ... 10/26/06 - 20060240627 - Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics In a method for manufacturing a MOS transistor, a MOS transistor isolation layer is formed within a semiconductor substrate to surround an area for forming the MOS transistor in the semiconductor substrate. Then, first impurities are introduced into the area of the semiconductor substrate to adjust a threshold voltage of ... 09/07/06 - 20060199341 - Methods of forming threshold voltage implant regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in ... 09/07/06 - 20060199340 - Methods of implanting dopant into channel regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in ... 07/06/06 - 20060148182 - Quantum well transistor using high dielectric constant dielectric layer A quantum well transistor or high electron mobility transistor may be formed using a replacement metal gate process. A dummy gate electrode may be used to define sidewall spacers and source drain contact metallizations. The dummy gate electrode may be removed and the remaining structure used as a mask to ... 07/06/06 - 20060148181 - Strained channel cmos device with fully silicided gate electrode A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region ... 06/29/06 - 20060141716 - Method for manufacturing a cell transistor of a semiconductor memory device Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor ... 03/02/06 - 20060046404 - Method for implanting a cell channel ion of semiconductor device A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to the bit line contact region in the cell region are subjected to a selective cell channel implant ... 01/26/06 - 20060019454 - Method for making a semiconductor device comprising a superlattice dielectric interface layer A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer ... 10/27/05 - 20050239256 - Shallow low energy ion implantation into pad oxide for improving threshold voltage stability A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately ... 10/20/05 - 20050233531 - Method of manufacturing semiconductor devices Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of an ion for adjusting the threshold ... 10/13/05 - 20050227444 - Method of fabricating self-aligned source and drain contacts in a double gate fet with controlled manufacturing of a thin si or non-si channel A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region ... 08/18/05 - 20050181565 - Threshold voltage adjustment for long channel transistors A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at ... 08/04/05 - 20050170591 - Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying ... 07/07/05 - 20050148144 - Selective post-doping of gate structures by means of selective oxide growth A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited ... 06/30/05 - 20050142772 - Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an oxide layer from a semiconductor substrate; forming a well region ... 06/30/05 - 20050142771 - Semiconductor device and method for fabricating the same A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion implantation areas having different depths in a ... 06/09/05 - 20050124122 - Semiconductor devices and methods for fabricating the same Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in the semiconductor substrate. Thus, the gate insulation layer is formed before ... ### FreshPatents.com Support |