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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Asymmetric AsymmetricAsymmetric patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.02/15/07 - 20070037353 - Efficient transistor structure An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first ... 01/04/07 - 20070004152 - Method for fabricating semiconductor device with step gated asymmetric recess A method for fabricating a semiconductor device with a step gated asymmetric recess is provided. The method includes: forming an organic bottom anti-reflective coating (BARC) layer over a substrate; forming a patterned mask over the organic BARC layer that expose selected portions of the organic BARC layer; etching the exposed ... 01/04/07 - 20070004151 - Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on ... 12/07/06 - 20060275990 - Semiconductor device and method of producing same A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain ... 11/30/06 - 20060270165 - Multi-layered spacer for lightly-doped drain mosfets A spacer for a lightly-doped drain MOSFET includes a first spacer layer adjacent to and in contact with a gate region and a lightly-doped region, a second spacer layer adjacent to and in contact with the first layer and a third spacer layer adjacent to and in contact with the ... 11/23/06 - 20060263988 - Semiconductor device Two vertical-type power MISFETs are formed over a semiconductor chip, a common drain electrode formed over a back surface of the semiconductor chip is electrically connected with a drain terminal via a conductive bonding material, source electrodes and gate electrodes formed over a surface of the semiconductor chip are respectively ... 09/21/06 - 20060211209 - Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device includes the steps of (a) forming a first insulating film pattern, which has a first portion and a second portion separated from the first portion through a first space, above a semiconductor substrate, (b) selectively forming a first impurity diffusion layer in a ... 09/14/06 - 20060205162 - Method for manufacturing semiconductor device with recess channels and asymmetrical junctions Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substrate, which includes storage nodes junction, the bit line junction, and channel ... 08/31/06 - 20060194395 - Metal hard mask method and structure for strained silicon mos transistors A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the ... 08/17/06 - 20060183289 - Back gate finfet sram A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a ... 08/03/06 - 20060172497 - Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top ... 05/25/06 - 20060110885 - Body having angle scaling A monolithic body having angle scaling is rotatable about an axis to measure the rotational position of a machine part. The body has a first annular region which has a flange-type configuration for connection to the machine part, and a second annular region on which the angle scaling is arranged, ... 04/13/06 - 20060079057 - Field effect transistor and method of fabricating the same Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of ... 12/29/05 - 20050287745 - Semiconductor device having multiple gate oxide layers and method of manufacturing thereof A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A ... 09/22/05 - 20050208725 - Semiconductor device having shared contact and fabrication method thereof Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a ... 08/25/05 - 20050186743 - Method for manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device capable avoiding occurrence of resist residue on a gate opening portion when forming the gate opening portion finely for injecting an impurity to form an asymmetric transistor during patterning of a gate electrode. The method of manufacturing the semiconductor device, in ... 06/23/05 - 20050136599 - Method of making high-voltage bipolar/cmos/dmos (bcd) devices A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of the following steps: (1) applying a first mask and forming at least one N-well in said p-type material therethrough; (2) applying ... ### FreshPatents.com Support |