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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Plural Gate Electrodes (e.g., Dual Gate, Etc.) Plural Gate Electrodes (e.g., Dual Gate, Etc.)Plural Gate Electrodes (e.g., Dual Gate, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/22/07 - 20070066019 - Surround gate access transistors with grown ultra-thin bodies A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short ... 03/15/07 - 20070059890 - Methods of manufacturing semiconductor thin film, electronic device and liquid crystal display device A semiconductor thin film manufacturing method includes: forming a semiconductor thin film on a substrate; forming a transcriptional body containing a metal element on a part thereof; bringing a part of the transcriptional body into contact with the semiconductor thin film, and transferring the metal element onto the semiconductor thin ... 03/01/07 - 20070048947 - Multi-structured si-fin and method of manufacture Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction ... 03/01/07 - 20070048946 - Transistor gate forming methods and integrated circuits A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited ... 12/07/06 - 20060275989 - Method of manufacturing liquid crystal display In a method of manufacturing a liquid crystal display, first, a panel assembly structure including a first substrate, a second substrate and several sealants connecting inner surfaces of the first and second substrate is provided. The first substrate includes several third substrates. The second substrate includes several fourth substrates corresponding ... 11/30/06 - 20060270164 - Method of making planar double gate silicon-on-insulator structures Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material ... 09/21/06 - 20060211208 - methods of forming gatelines and transistor devices The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of ... 08/24/06 - 20060189085 - Method of forming dual polysilicon gate of semiconductor device In a method of forming a dual polysilicon gate of a semiconductor device, a polysilicon layer is formed on a substrate divided into an NMOS region and a PMOS region. Then, a p-type impurity is implanted in the PMOS region. A thermal annealing process is performed that causes generation of ... 08/03/06 - 20060172496 - Double-gate fets (field effect transistors) A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from ... 07/20/06 - 20060160313 - Semiconductor device and method of manufacturing the same An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulation layer; forming pocket regions by a pocket ion implantation process using the gate electrode ... 07/13/06 - 20060154424 - Method of manufacturing a split-gate flash memory device A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area. ... 07/13/06 - 20060154423 - Methods of forming structure and spacer and related finfet Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top ... 06/22/06 - 20060134868 - Double gate field effect transistor and method of manufacturing the same Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming ... 06/01/06 - 20060115947 - Planarizing method for forming fin-fet device A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket ... 05/18/06 - 20060105529 - Methods of forming mos transistors having buried gate electrodes therein Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode ... 03/02/06 - 20060046401 - Forming integrated circuits with replacement metal gate electrodes In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of ... 02/09/06 - 20060030109 - Method to produce highly doped polysilicon thin films The present invention describes a method of forming a highly doped polysilicon film. According to an embodiment of the present invention, a first silicon film is formed on a substrate. The first silicon film is then doped. Next, a second silicon film is formed on the doped first silicon film. ... 12/22/05 - 20050282341 - High-temperature stable gate structure with metallic electrode The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has ... 11/24/05 - 20050260816 - Method for removing a semiconductor layer A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approximately 1,000. In one embodiment, the second ... 11/17/05 - 20050255657 - Methods of forming a nonvolatile memory device having a local sonos structure that use spacers to adjust the overlap between a gate electrode and a charge trapping layer A nonvolatile memory device is formed by forming a first oxide layer on a substrate. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. The second oxide layer is patterned so as to expose the nitride layer. A first ... 11/17/05 - 20050255656 - Field effect transistor (fet) devices and methods of manufacturing fet devices In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer ... 11/10/05 - 20050250285 - Fin field effect transistor device and method of fabricating the same Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer ... 11/03/05 - 20050245033 - Method for forming gate of semiconductor device Disclosed is a method for forming a gate of a semiconductor device capable of preventing a bridge from being created between adjacent gates due to a nitride polymer. The method includes the steps of forming a gate oxide film, a gate poly-Si film, and a gate W film successively on ... 10/20/05 - 20050233525 - Gate electrode for a semiconductor fin device A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method ... 09/15/05 - 20050202639 - Method of manufacturing memory device comprising gate having uniformly distributed silicon nano dots Provided is a method of manufacturing a memory device that comprises a gate including uniformly distributed silicon nano dots. The method includes forming a gate on a substrate, the gate including, stacked in sequence an insulating film, nano dot layers separated by a predetermined lateral distance, and a conductive film ... 08/25/05 - 20050186742 - Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are ... 07/07/05 - 20050148143 - Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while ... 06/09/05 - 20050124120 - Method and circuit for multiplying signals with a transistor having more than one independent gate structure A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between ... ### FreshPatents.com Support |