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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Making Plural Insulated Gate Field Effect Transistors Having Common Active Region Making Plural Insulated Gate Field Effect Transistors Having Common Active RegionMaking Plural Insulated Gate Field Effect Transistors Having Common Active Region patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/15/07 - 20070059888 - Semiconductor integrated circuit device and manufacturing method thereof A semiconductor integrated circuit device having a pair of adjacent MOS transistors and a contact plug 33, buried into a contact hole formed by a self-aligned contact process using a silicon nitride film as an etching stopper and electrically connected to diffusion layers 2 and 3 constituting the MOS transistor ... 02/22/07 - 20070042554 - Methods of forming sram cells having landing pad in contact with upper and lower cell gate patterns SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting ... 12/21/06 - 20060286752 - Method of fabricating non-volatile memory A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. ... 11/02/06 - 20060246669 - Method for fabricating semiconductor devices having dual gate oxide layer A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the ... 10/12/06 - 20060228862 - Fet design with long gate and dense pitch A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with ... 07/20/06 - 20060160312 - Gate electrode for finfet device In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having ... 06/29/06 - 20060141715 - Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion ... 06/15/06 - 20060128104 - Nrom memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store ... 06/15/06 - 20060128103 - Nrom memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store ... 04/13/06 - 20060079055 - Method of forming a split programming virtual ground sonos memory A method of forming an SPVG SONOS memory. First, a substrate having a well and a plurality of select gate structures is provided. Then, a plurality of sacrificial spacers are formed alongside each select gate structure, and an implantation process is performed to form a doped region in the well ... 03/30/06 - 20060068552 - Method of manufacturing semiconductor device In a semiconductor device manufacturing method of the present invention, a polysilicon film and a silicon nitride film are deposited on an upper surface of an epitaxial layer. Patterning is performed so that the polysilicon film and the silicon nitride film are left in regions in which a LOCOS oxide ... 03/02/06 - 20060046398 - Low resistance peripheral local interconnect contacts with selective wet strip of titanium Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. ... 01/26/06 - 20060019450 - Semiconductor device and method for manufacturing the same An exemplary method for manufacturing a semiconductor device includes: forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer, respectively formed thereabove and one or more junction regions formed therein so as to fill a full height of a gap between gates; ... ### FreshPatents.com Support |