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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Making Plural Insulated Gate Field Effect Transistors Of Differing Electrical Characteristics Making Plural Insulated Gate Field Effect Transistors Of Differing Electrical CharacteristicsMaking Plural Insulated Gate Field Effect Transistors Of Differing Electrical Characteristics patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/29/07 - 20070072376 - Strained-induced mobility enhancement nano-device structure and integrated process architecture for cmos technologies A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within ... 03/01/07 - 20070048944 - Low voltage trigger and save area electrostatic discharge device Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD ... 02/08/07 - 20070032022 - Mask read only memory (rom) and method of fabricating the same The Mask ROM includes a plurality of doped lines arranged on a substrate of a first conductivity. The doped lines have a second conductivity. In addition, the Mask ROM further includes an insulation film covering the substrate, a plurality of interconnections intersecting the doped lines in parallel and arranged on ... 02/08/07 - 20070032021 - Method for forming a gate dielectric of a semiconductor device Disclosed is a method for forming a gate dielectric in a semiconductor device. The present method includes forming a first dielectric layer on a semiconductor substrate; removing a portion of the first dielectric layer to expose a portion of the substrate; forming a nitride layer on the exposed portion of ... 02/01/07 - 20070026614 - Cmos-compatible high-performance microscanners, including structures, high-yield simplified fabrication methods and applications The present invention relates to systems and methods for fabricating microscanners. The fabrication processes employed pursuant to some embodiments are compatible with well known CMOS fabrication techniques, allowing devices for control, monitoring and/or sensing to be integrated onto a single chip. Both one- and two-dimensional microscanners are described. Applications including ... 01/25/07 - 20070020859 - Method of making non-volatile field effect devices and arrays of same Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the ... 01/25/07 - 20070020858 - Layout structure of mos transistors and methods of disposing mos transistors on an active region In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench ... 01/04/07 - 20070004150 - Electrostatic discharge protection semiconductor structure An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit finction and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design ... 12/28/06 - 20060292803 - High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate ... 12/07/06 - 20060275988 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and ... 11/30/06 - 20060270163 - Semiconductor chip with flip chip contacts, and method for producing semiconductor chip with flip chip contacts A semiconductor chip includes flip chip contacts that are arranged on contact surfaces of an active top side of the semiconductor chip. The contact surfaces are surrounded by a passivation layer that covers the active top side while leaving exposed the contact surfaces. The passivation layer includes thickened portions that ... 11/30/06 - 20060270162 - High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate ... 11/30/06 - 20060270161 - Method of reducing charging damage to integrated circuits during semiconductor manufacturing A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device ... 11/23/06 - 20060263985 - Method of fabricating a semiconductor device A method of fabricating a semiconductor device to prevent the profiles of source/drain regions from being deformed due to the thermal budget. The method can simplify the overall process of fabricating a semiconductor device by reducing the number of processing steps of forming a photoresist pattern as an ion implantation ... 11/09/06 - 20060252210 - Method for fabricating semiconductor device and wire with silicide A method for fabricating a wire with silicide is disclosed. First, a conductive layer is formed on a substrate. And, a hard mask layer is formed on the conductive layer. Then, the hard mask layer is used as a mask to remove a portion of the conductive layer. Afterwards, a ... 10/05/06 - 20060223266 - Method of forming an electronic device A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during ... 09/21/06 - 20060211206 - Electronic devices including non-volatile memory and processes for forming the same A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By ... 09/07/06 - 20060199339 - Method and structure in the manufacture of mask read only memory A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, ... 08/31/06 - 20060194394 - Mask rom, method for fabricating the same, and method for coding the same A mask ROM, a method for fabricating the same and a method for coding the same are disclosed. The method for forming the mask ROM maximizes packing density and integration of a device. The mask ROM includes a semiconductor substrate having a device isolation region and an active region, BN ... 08/31/06 - 20060194393 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film ... 08/24/06 - 20060189083 - Field effect transistor with etched-back gate dielectric An ultrathin high-k gate dielectric made for use in a field-effect transistor is provided. The gate dialectric is made by depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to ... 08/10/06 - 20060177984 - Method for manufacturing semiconductor elemental device The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised of silicon, comprising the steps of implanting ... 08/03/06 - 20060172495 - Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation ... 07/27/06 - 20060166445 - Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate ... 07/20/06 - 20060160311 - Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. ... 06/29/06 - 20060141714 - Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a ... 06/29/06 - 20060141713 - Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned ... 06/08/06 - 20060121677 - Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain ... 05/18/06 - 20060105528 - High voltage mosfet having si/sige heterojunction structure and method of manufacturing the same Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a ... 05/18/06 - 20060105527 - Semiconductor device and manufacturing method therefor A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping ... 04/20/06 - 20060084230 - Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth ... 04/20/06 - 20060084229 - Post high voltage gate oxide pattern high-vacuum outgas surface treatment The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within ... 03/30/06 - 20060068551 - Method for embedding nrom A method for embedding non-volatile memories with logic circuitry, without changing performance of both the logic circuitry and the NVM elements (and/or without changing a sequence of manufacturing steps for both the logic circuitry and the NVM elements). The embedding process includes insertion of NVM device and array process steps ... 03/30/06 - 20060068550 - Independently accessed double-gate and tri-gate transistors in same process flow A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member ... 02/09/06 - 20060030107 - Cmos compatible process with different-voltage devices A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. ... 01/26/06 - 20060019449 - Reduction of field edge thinning in peripheral devices A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the ... 01/12/06 - 20060008995 - Method for manufacturing semiconductor device On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural ... 12/22/05 - 20050282340 - Semiconductor apparatus with improved esd withstanding voltage A semiconductor apparatus having an outer ESD protective circuit corresponding to each external connection terminal, the outer ESD protective circuit being formed in a peripheral region around the external connection terminals. The outer ESD protective circuit discharges electrostatic voltage from the external connection terminal and avoids the damaging of an ... 12/01/05 - 20050266644 - Method of manufacturing semiconductor device having multiple gate oxide films A method of manufacturing a semiconductor device includes forming a first insulating film having a first thickness in a first region on a semiconductor substrate, forming a first gate electrode on the first insulating film, and forming a second insulating film having a second thickness different from the first thickness ... 12/01/05 - 20050266643 - Memory with recessed devices A memory cell includes devices having associated isolation recesses of differing magnitudes. The effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses. In an SRAM cell, a latch transistor has a larger effective ... 11/24/05 - 20050260815 - Step gate electrode structures for field-effect transistors and methods for fabricating the same A method is disclosed for forming at least two semiconductor devices with different gate electrode thicknesses. After forming a gate dielectric region, and determining whether a first or second device formed on the gate dielectric region expects a relatively faster gate dopant diffusion rate, a gate electrode layer is formed ... 11/03/05 - 20050245032 - Application of a protective cover to an ophtalmological instrument part An application system and an application method for applying a flexible protective cover (1) to the frustoconical tip (21) of an ophthalmological instrument part (2) are proposed. The protective cover (1) is arranged in the depression (31) of an applicator part (3) above a stamp (34) made of compressible material. ... 10/13/05 - 20050227440 - Semiconductor device and its manufacturing method A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region ... 10/13/05 - 20050227439 - Tri-gate low power device and method for manufacturing the same The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric ... 09/29/05 - 20050215014 - Complementary metal oxide semiconductor (cmos) transistors having three-dimensional channel regions and methods of forming same An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also ... 09/15/05 - 20050202638 - Method of reducing step height A method of reducing substrate step height. The method includes providing a substrate having a low-voltage device area and high-voltage device area divided by an isolation structure, forming an oxidation mask at least approximately 500 Å thick over the low-voltage device area and parts of the isolation structure, forming a ... 08/25/05 - 20050186741 - Sonos embedded memory with cvd dielectric An embedded semiconductor memory is fabricated by: forming diffusion bit line regions in a semiconductor substrate; then thermally oxidizing the upper surface of the substrate, thereby forming a bottom oxide layer over the substrate and simultaneously forming bit line oxide regions over each of the diffusion bit line regions; and ... 08/04/05 - 20050170588 - Method for forming multi-level mask rom cell and nand multi-level mask rom The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing ... 07/28/05 - 20050164456 - Method for fabricating an nrom memory cell array In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the ... 07/14/05 - 20050153512 - Method of forming an eprom cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... 06/09/05 - 20050124119 - Open drain input/output structure and manufacturing method thereof in semiconductor device The present invention relates to an open drain input/output structure and manufacturing method thereof in which a n-channel depletion transistor for pull-up resistance can be used like an enhancement transistor without impurity ion implantation process when being formed an open drain input/output terminal. An open drain input/output structure in a ... 06/02/05 - 20050118765 - Semiconductor device and method of manufacturing thereof This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration ... 06/02/05 - 20050118764 - Forming gate oxides having multiple thicknesses Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may ... ### FreshPatents.com Support - Terms & Conditions |