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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Vertical Channel Vertical ChannelVertical Channel patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082448 - Semiconductor devices having transistors with vertical channels and method of fabricating the same In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4 F2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupation area, repeatedly aligned along a first ... 03/22/07 - 20070066018 - Methods of fabricating vertical channel field effect transistors having insulating layers thereon A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain ... 03/15/07 - 20070059886 - System and method for automatically calculating parameters of an mosfet A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values inputted, and for calculating parameters of the MOSFET according to the input values. The parameter calculating system includes an operation selecting module ... 03/01/07 - 20070048943 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning. ... 03/01/07 - 20070048942 - Methods of forming field effect transistors on substrates The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and ... 02/22/07 - 20070042549 - Semiconductor device having reduced effective substrate resistivity and associated methods A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical ... 01/25/07 - 20070020855 - Semiconductor device having vertical channels and method of manufacturing the same A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The ... 01/04/07 - 20070004149 - Method for producing a vertical field effect transistor A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility. ... 11/23/06 - 20060263984 - Vertical nanotransistor, method for producing the same and memory assembly A vertical nano-transistor having a source region, a drain region, a gate region and a semiconductor channel region between the source region and the drain region, the gate region being constituted by a metal film into which the transistor is embedded in such a manner that the gate region and ... 10/26/06 - 20060240625 - Power semiconductor device having improved performance and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region. ... 10/05/06 - 20060223265 - Vertical transistor of semiconductor device and method for forming the same A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an ... 08/31/06 - 20060194392 - Mis-type semiconductor device A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base ... 08/31/06 - 20060194391 - Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of ... 08/24/06 - 20060189081 - Ldmos device and method of fabrication of ldmos device A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having ... 07/20/06 - 20060160309 - Method of manufacturing a superjunction device with conventional terminations A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched into an active region of the substrate forming a plurality of ... 05/18/06 - 20060105526 - Method of fabricating a bottle trench and a bottle trench capacitor A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent ... 04/20/06 - 20060084228 - Low thermal resistance semiconductor device and method therefor A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device. ... 03/23/06 - 20060063334 - Fin fet diode structures and methods for building FinFET diode structures and methods are provided for building the FinFET diode structures. A FinFET diode structure is created by implanting a diffusion Fin on a first side with a P+ dopant and on a second side with a N+ dopant providing a P+N+ diode structure. ... 03/02/06 - 20060046394 - Forming a vertical transistor The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material ... 03/02/06 - 20060046393 - Semiconductor device and method for manufacturing the same A semiconductor device includes a gate electrode formed on a semiconductor layer, source and drain layers formed in the semiconductor layer and disposed on both sides of the gate electrode, and a field plate disposed at the back of the semiconductor layer with an insulating layer provided therebetween. ... 03/02/06 - 20060046392 - Methods of forming vertical transistor structures The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical ... 03/02/06 - 20060046391 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning. ... 02/09/06 - 20060030106 - Gate conductor isolation and method for manufacturing same A method for processing a semiconductor device includes providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate. The method includes stripping the ... 02/02/06 - 20060024890 - Power mos device with improved gate charge performance A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a ... 01/12/06 - 20060008993 - Method of manufacturing flash memory device Disclosed is a method of manufacturing a flash memory device using a STI process. Isolation films of a projection structure becomes isolation films of a nipple structure by means of a slant ion implant process and a wet etching process. A polysilicon layer is removed until the tops of the ... 12/08/05 - 20050272208 - Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. ... 10/27/05 - 20050239252 - Methods of forming integrated circuit devices having field effect transistors of different types in different device regions A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect transistor in a peripheral circuit portion of the semiconductor substrate. The non-planar field-effect transistor may be selected from the group of a ... 10/13/05 - 20050227438 - Semiconductor device and method of manufacturing same A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with ... 10/06/05 - 20050221563 - Enhanced substrate contact for a semiconductor device A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into ... 09/22/05 - 20050208723 - Semiconductor device including a channel stop structure and method of manufacturing the same It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). ... 09/15/05 - 20050202636 - Single-pole component manufacturing The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie ... 09/15/05 - 20050202635 - Method for fabricating vertical transistor A method for fabricating a vertical transistor including forming a first junction area in a semiconductor substrate, forming a polysilicon layer by using an epitaxial growth in the substrate, forming a second junction area in the polysilicon layer, and forming a plug junction area in the polysilicon layer, the plug ... 09/15/05 - 20050202634 - Method for forming a top oxide with nitride liner A method for forming a top oxide for a deep trench memory device comprising a poly stud above a polysilicon fill in a deep trench and an isolation region in a portion of the deep trench, comprises forming an etch support nitride liner by low-pressure chemical vapor deposition over the ... 09/01/05 - 20050191809 - Common mosfet process for plural devices A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusion stage for forming very low concentration mesas ... 06/30/05 - 20050142766 - Method of fabricating an ultra-narrow channel semiconductor device A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region of the ... ### FreshPatents.com Support |