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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) > Multiple Interelectrode Dielectrics Or Nonsilicon Compound Gate Insulator Multiple Interelectrode Dielectrics Or Nonsilicon Compound Gate InsulatorMultiple Interelectrode Dielectrics Or Nonsilicon Compound Gate Insulator patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077712 - Methods of fabricating non-volatile memory devices including nanocrystals Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic ... 03/08/07 - 20070054453 - Methods of forming integrated circuit memory devices having a charge storing layer formed by plasma doping Methods of forming an integrated circuit memory device include forming a dielectric layer on a substrate and forming a charge storing layer on an upper surface of the dielectric layer using a plasma doping process with a remaining portion of the dielectric layer under the charge storing layer defining a ... 02/15/07 - 20070037351 - Method of fabricating a resistance based memory device and the memory device Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device ... 02/08/07 - 20070032016 - Protective layer in memory device and method therefor A method protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, die protective layer being adapted to absorb electromagnetic wave energy ... 02/01/07 - 20070026611 - Method for manufacturing semiconductor devices A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al2O3 and a polysilicon or SiO2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl3, ... 01/04/07 - 20070004147 - Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second ... 01/04/07 - 20070004146 - Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step ... 12/28/06 - 20060292800 - Ono formation of semiconductor memory device and method of fabricating the same A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on ... 12/21/06 - 20060286749 - Method of fabricating non-volatile memory A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. ... 12/14/06 - 20060281257 - Stack gate structure of flash memory device and fabrication method for the same A nonvolatile memory device has a floating gate with its top and side surfaces covered by ONO film to improve the data retention of the floating gate. The ONO film has upper and lower silicon dioxide layers interposed by silicon nitride layer thinner than the oxide layers. A method includes ... 11/02/06 - 20060246665 - Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and ... 10/19/06 - 20060234452 - Non-volatile memory and fabricating method thereof A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control ... 09/14/06 - 20060205157 - Non-volatile memory and method for fabricating the same A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive ... 09/07/06 - 20060199336 - Split gate non-volatile memory devices and methods of forming same Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance. ... 08/24/06 - 20060189080 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: forming at least two gate patterns over a substrate; forming a first sidewall layer over on entire of the substrate structure including gat patterns; forming an insulation layer over the first sidewall layer; selectively removing the insulation layer ... 07/20/06 - 20060160308 - Method of forming a gate of a flash memory device The present invention provides a method of forming a gate in a flash memory device. The method includes: forming a oxide layer on a semiconductor substrate; forming a stacked structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate by patterning them on the ... 07/20/06 - 20060160307 - Method of driving memory device to implement multiple states A method of driving a multi-state organic memory device which includes an organic memory layer between upper and lower electrodes. The method comprises continuously applying voltages having different polarities to conduct switching into a low resistance state, and applying a single pulse to conduct switching into a high resistance state. ... 06/29/06 - 20060141710 - Nor-type flash memory device of twin bit cell structure and method of fabricating the same A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact. ... 06/29/06 - 20060141709 - Method for programming multi-level nitride read-only memory cells A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride ... 06/22/06 - 20060134866 - Non-volatile memory and method for fabricating the same A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive ... 05/04/06 - 20060094191 - Methods of manufacturing a semiconductor device including a dielectric layer including zirconium A method of manufacturing a semiconductor device can include forming a tunnel oxide layer on a substrate, forming a floating gate on the tunnel oxide layer and forming a dielectric layer pattern on the floating gate using an ALD process. The dielectric layer pattern can include a metal precursor that ... 04/13/06 - 20060079053 - Nrom device and method of making same A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments ... 03/30/06 - 20060068549 - Image display device An image display device includes a first substrate having a phosphor screen, and a second substrate opposed to the first substrate across a gap and having a plurality of electron emission sources which excite the phosphor screen. A spacer assembly which supports atmospheric load acting on the first and second ... 12/08/05 - 20050272207 - Complementary analog bipolar transistors with trench-constrained isolation diffusion A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density ... 12/01/05 - 20050266640 - Method of forming a dielectric layer and method of manufacturing a nonvolatile memory device using the same A method of forming a dielectric layer having a reduced thickness according to embodiments of the invention includes forming a lower oxide layer on a substrate, and forming a nitride layer on the lower oxide layer. Then, a preliminary oxide layer is formed on the nitride layer. A radical oxidation ... 10/06/05 - 20050221562 - Method for manufacturing semiconductor device having thick insulating layer under gate side walls A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide ... 08/11/05 - 20050176203 - [method of fabricating non-volatile memory cell ] A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate ... 07/21/05 - 20050158954 - Method for fabricating semiconductor device In a method for fabricating a semiconductor device in which a semiconductor memory element having an ONO film and a CMOS part are formed on a single semiconductor substrate, a CMOS gate-oxidation step is performed several times. Thereafter, a bit line diffusion layer and a bit line oxide film are ... 06/30/05 - 20050142762 - Methods of fabricating non-volatile memory devices Methods of fabricating non-volatile memory devices are disclosed. The resulting non-volatile memory devices include an additional protection film is formed on a control gate pattern to enable the control gate pattern to have a regular and smooth profile regardless of an etching process progressed intensively for removing an active cell ... 06/30/05 - 20050142761 - Method of fabricating split gate flash memory device A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a first gate pattern covered with a cap layer on a semiconductor substrate in an active area, and forming an etchant-resistant layer covering one side of the first gate pattern, ... 06/30/05 - 20050142760 - Method of fabricating semiconductor device The present invention provides a method of fabricating a semiconductor device, by which leakage current is minimized and by which drivability of transistor is sustained. The present invention includes forming a gate pattern having a gate oxide layer underneath on a semiconductor substrate, forming a first oxide layer on the ... 06/23/05 - 20050136596 - Semiconductor constructions The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer ... ### FreshPatents.com Support |