REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) > Including Forming Gate Electrode In Trench Or Recess In Substrate Including Forming Gate Electrode In Trench Or Recess In SubstrateIncluding Forming Gate Electrode In Trench Or Recess In Substrate patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077711 - Fabricating method of an non-volatile memory A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under ... 03/01/07 - 20070048941 - Transistor gate forming methods and transistor structures A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within ... 01/25/07 - 20070020852 - Semiconductor memory device with a stacked gate including a floating gate and a control gate A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS ... 01/25/07 - 20070020851 - Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench and a method of using the same A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion ... 01/25/07 - 20070020850 - Method for manufacturing semiconductor device and semiconductor device A method for manufacturing a semiconductor device including the steps of: forming a hole having a predetermined depth in a semiconductor layer of a first conductivity type in correspondence with a drain region, the semiconductor layer being formed on a semiconductor substrate; forming a diffusion source layer containing impurities of ... 01/18/07 - 20070015333 - Method for manufacturing silicon carbide semiconductor devices A method of manufacturing a semiconductor device is disclosed that includes the treating the surface of a SiC semiconductor substrate prior to forming a gate oxide film on the SiC semiconductor substrate in order to etch the SiC semiconductor substrate by several nm to 0.1 μm with hydrogen in a ... 01/11/07 - 20070010058 - Method and apparatus for a self-aligned recessed access device (rad) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. ... 01/04/07 - 20070004145 - Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate ... 10/19/06 - 20060234451 - Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements ... 10/12/06 - 20060228861 - Partially recessed dram cell structure and method of making the same A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed ... 09/21/06 - 20060211204 - Non-volatile memory and method of fabricating the same A method for fabricating a non-volatile memory is disclosed. First, a semiconductor device is formed in a substrate, and the top of the semiconductor device is higher than the surface of the substrate. Then, a first dielectric layer is formed on the substrate, and the first dielectric layer covers the ... 09/21/06 - 20060211203 - Semiconductor device and method of manufacturing the same Disclosed herein are a method of manufacturing a semiconductor device, which can prevent a stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconductor device manufactured thereby. The method comprises ... 07/27/06 - 20060166442 - Method for manufacturing semiconductor device In a method for manufacturing a semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer and the substrate are patterned to form a device isolation layer defining an active region. The mask layer and the substrate are patterned in the active region to form a ... 07/06/06 - 20060148174 - Method for forming recess gate of semiconductor device A method for forming a recess gate of a semiconductor device is disclosed. The method for forming a recess gate of a semiconductor device comprises forming a polysilicon layer pattern covering a contact region on a semiconductor substrate, etching a predetermined thickness of the semiconductor substrate in the active region ... 06/29/06 - 20060141708 - Non-volatile memory device with buried control gate and method of fabricating the same In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a ... 06/15/06 - 20060128100 - Semiconductor device and a method of producing the same A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to ... 03/23/06 - 20060063331 - Nonvolatile memory devices with trenched side-wall transistors and method of fabricating the same A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is ... 03/02/06 - 20060046389 - Manufacturing process and structure of integrated circuit The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only ... 02/09/06 - 20060030104 - Integrating n-type and p-type metal gate transistors At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates. ... 01/12/06 - 20060008991 - Trenched semiconductor devices and their manufacture In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the ... 12/29/05 - 20050287743 - Method of manufacturing semiconductor device having recess channel structure Disclosed herein is a method of manufacturing a semiconductor device having a recess channel structure, which prevents misalignment of a source/drain, thereby being capable of achieving an improvement in the drive-ability of a gate and preventing a degradation in characteristics of the semiconductor device due to a hot carrier effect. ... 12/15/05 - 20050277254 - Methods of forming device with recessed gate electrodes Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active ... 09/29/05 - 20050215010 - Method for fabricating gate electrodes in a field plate trench transistor, and field plate trench transistor A method for fabricating gate electrodes (7) in a field plate trench transistor (1) having a cell array with a plurality of trenches (3) and a plurality of mesa regions (8) arranged between the trenches comprises the following steps: application of a gate electrode layer (7) to the cell array ... 09/22/05 - 20050208722 - Trench-gate semiconductor device and method of manufacturing A trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate (24) provided below the trenched gate (8) is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove (28a) into the semiconductor body (20) for receiving the gate (8), ... 09/08/05 - 20050196923 - Sonos memory cells and arrays and method of forming the same A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer ... 07/21/05 - 20050158953 - Method for fabricating an nrom memory cell arrangement In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers ... ### FreshPatents.com Support |