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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) > Including Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) Including Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.)Including Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/15/07 - 20070059883 - Method of fabricating trap nonvolatile memory device A method of fabricating a floating trap type nonvolatile memory device is provided. The method includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally ... 02/01/07 - 20070026610 - Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions ... 01/04/07 - 20070004144 - Method of fabricating dual gate oxide layer having different thickness in the cell region and the peripheral region In fabricating a dual gate oxide layer, a first gate oxide layer is first formed on a semiconductor substrate, which has a cell region and a peripheral region. The first gate oxide layer is removed in the peripheral region. A second gate oxide layer is formed on the substrate using ... 12/28/06 - 20060292799 - Memory embedded semiconductor device and method for fabricating the same A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed ... 11/16/06 - 20060258099 - Semiconductor memory device and method of manufacturing the same A method of manufacturing a semiconductor memory device is provided. The method includes: providing a semiconductor substrate, forming a cell transistor on the semiconductor substrate, and forming a SiON layer with a refractive index of about 1.8 or less on the cell transistor. ... 11/16/06 - 20060258098 - Method of fabricating semiconductor device A method of fabricating semiconductor devices. Upon formation of a trench for isolation in a cell region, a hard mask film is used as an etch mask. It is thus possible to prevent attacks of a lower layer due to deformation or loss of the etch mask. ... 10/26/06 - 20060240624 - Single transistor ram cell and method of manufacture A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped ... 09/21/06 - 20060211202 - Forming metal silicide on silicon-containing features of a substrate A metal suicide layer is formed on silicon-containing features of a substrate in a chamber. A metal film is sputter deposited on the substrate and a portion of the sputter deposited metal film is silicided. In the process, sputtering gas is energized by applying an electrical bias potential across the ... 09/07/06 - 20060199335 - Electronic devices including non-volatile memory structures and processes for forming the same An electronic device can include an NVM structure and a gate electrode outside an NVM array. In one embodiment, a first gate dielectric layer and a first gate electrode layer are formed before forming NVM cells within an NVM array. The first gate electrode layer helps to protect the first ... 07/20/06 - 20060160306 - Method for forming trench gate dielectric layer A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor ... 07/06/06 - 20060148173 - Method for manufacturing electronic memory devices integrated in a semiconductor substrate including non-volatile memory matrix and associated circuitry The method is for manufacturing electronic memory devices on a semiconductor substrate including a non-volatile memory matrix and associated circuitry. The method includes forming a first insulation layer, a conductive layer and a second insulation layer. A resist mask is formed corresponding with the memory matrix to define a predetermined ... 06/15/06 - 20060128099 - Method of fabricating flash memory device including control gate extensions A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch ... 05/04/06 - 20060094190 - Semiconductor device, pattern design method of a semiconductor device and program for a pattern design method According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy pattern region and a dummy pattern prohibition ... 01/12/06 - 20060008990 - Method for fabricating cell transistor of flash memory A method for fabricating a cell transistor of a flash memory including a device isolation film is disclosed, to prevent the mouse bite and the residue of a gate electrode, which includes the steps of forming a moat pattern of STI structure on a semiconductor substrate; forming a shallow trench ... 01/05/06 - 20060003530 - Semiconductor memory device and method for fabricating the same The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed ... 01/05/06 - 20060003529 - Dielectric storage memory cell having high permittivity top dielectric and method therefor A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and ... 11/03/05 - 20050245031 - Method of manufacturing eeprom cell A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling ... 10/27/05 - 20050239251 - Semiconductor device and method for fabricating the same A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the ... 10/27/05 - 20050239250 - Ultra dense non-volatile memory array Twin side-by-side non-volatile memory transistors have a common T-shaped control gate over mirror image floating gates sharing a common subsurface electrode between the floating gates. Select transistors on either side of the transistor pair, in combination with the common control gate allow selection of individual transistors in an array of ... 10/06/05 - 20050221561 - Semiconductor integrated circuit device and method for manufacturing the same A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate. Further, a column switch region is provided adjacent to the ROM region. MOS transistors in the ROM region and channel regions of ... 08/18/05 - 20050181563 - Fabrication method for flash memory source line and flash memory A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, and a third insulation ... 06/30/05 - 20050142759 - Methods for fabricating semiconductor devices Methods for fabricating semiconductor devices are disclosed. An illustrated method includes: etching a semiconductor substrate to form a trench, forming an ONO film on the semiconductor substrate, removing the ONO film from the upper surface of the semiconductor substrate while leaving the ONO film on an inside wall surface of ... 06/30/05 - 20050142758 - Method of fabricating split gate flash memory device A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a dielectric layer on an active area of a semiconductor substrate, forming a first gate covered with a cap layer on the dielectric layer, and forming an insulating layer on ... 06/30/05 - 20050142757 - Methods of fabricating nonvolatile memory device A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an active region of the semiconductor substrate to form ... 06/30/05 - 20050142756 - Semiconductor device and method for fabricating the same A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell ... 06/30/05 - 20050142755 - Method for manufacturing a non-volatile memory device The present invention relates to a method for manufacturing a nonvolatile memory device, which can prevent damage to a silicon substrate and reduce a number of process steps by forming a logic gate electrode and cell control gate electrode at the same time instead of an SAE etching process. ... ### FreshPatents.com Support |