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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Including Passive Device (e.g., Resistor, Capacitor, Etc.) > Capacitor > Stacked Capacitor Stacked CapacitorStacked Capacitor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/15/07 - 20070059881 - Atomic layer deposited zirconium aluminum oxide A dielectric layer having atomic layer deposited zirconium aluminum oxide and a method of fabricating such a dielectric layer may produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The zirconium aluminum oxide may be formed in an atomic layer deposition process that includes ... 03/15/07 - 20070059880 - Hsg process and process of fabricating large-area electrode A hemispherical silicon grain (HSG) process is described. A doped poly-Si layer is formed on a substrate, and then an oxidative gas is used to oxidize the surface of the doped poly-Si layer to form an oxide layer. An a-Si layer is then formed on the oxide layer, and the ... 03/01/07 - 20070048933 - Semiconductor device manufacturing method Provided is a semiconductor device manufacturing method including the steps of: forming an n-type impurity diffusion region by ion-implanting arsenic into a capacitor formation region of a silicon substrate under a condition that a beam current is not less than 1 μA but less than 3 mA; forming a capacitor ... 03/01/07 - 20070048932 - Semiconductor constructions comprising conductive structures, and methods of forming conductive structures The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the ... 02/22/07 - 20070042543 - Method for manufacturing semiconductor device A method for manufacturing a semiconductor device, the method comprising the steps of: (a) forming a titanium layer above a substrate; (b) forming a barrier layer above the titanium layer; (c) changing the titanium layer to a titanium nitride layer by conducting a heat treatment in a nitrogen containing atmosphere; ... 02/15/07 - 20070037349 - Method of forming electrodes To form a semiconductor device, a plurality of upwardly extending conductors can be formed. The conductors extend outward from a surface of a semiconductor body, adjacent ones of the conductors being separated from each other by a separating material. At least one support structure is formed between adjacent ones of ... 02/01/07 - 20070026604 - Semiconductor device and fabrication method therefor A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy ... 01/25/07 - 20070020844 - Method for fabricating bit line of memory device A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer. ... 01/04/07 - 20070004133 - Capacitor for a semiconductor device and method of fabricating same A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first ... 01/04/07 - 20070004132 - Dram memory device The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact ... 01/04/07 - 20070004131 - Methods for forming shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the ... 12/28/06 - 20060292791 - Semiconductor integrated circuit device and method for manufacturing the same In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, ... 12/28/06 - 20060292790 - Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 ... 12/14/06 - 20060281253 - Semiconductor local interconnect and contact An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed ... 12/14/06 - 20060281252 - Metal interconnect for capacitor A method and implementation for coupling a high current electrode to an energy storage device is disclosed. ... 12/14/06 - 20060281251 - Method for manufacturing gate dielectric layer A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A ... 12/14/06 - 20060281250 - 6f2 access transistor arrangement and semiconductor memory device An access transistor arrangement is provided for a 6F2 stacked capacitor DRAM memory cell layout with shared bit line contacts. The access transistors are arranged in pairs along semiconductor lines. The two transistors of each pair of transistors are arranged laterally reversed opposing the respective common bit line section. Each ... 12/07/06 - 20060275982 - Semiconductor memory device, semiconductor device, and method for production thereof Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to form the gate electrode. Hence the resulting devices have a ... 12/07/06 - 20060275981 - Memory and method for fabricating it Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric ... 12/07/06 - 20060275980 - Semiconductor device and method for manufacturing the same A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein ... 11/30/06 - 20060270155 - Semiconductor device having diffusion barrier layer containing chrome and method for fabricating the same A semiconductor device is provided which is capable of preventing a constitutional material of a diffusion barrier layer from diffusing into a bottom electrode during a high thermal process and of preventing an increase in contact resistance of a contact plug by suppressing mutual diffusions of the constitutional material of ... 11/30/06 - 20060270154 - Semiconductor device having cell transistor with recess channel structure and method of manufacturing the same The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an ... 11/30/06 - 20060270153 - Method for fabricating semiconductor device Disclosed herein is a method for fabricating a memory device. According to the present invention, a device isolation film is etched using a mask partially exposing a channel region and the device isolation film adjacent thereto during the etching process of the recess gate region, and a semiconductor substrate in ... 11/30/06 - 20060270152 - Method of manufacturing semiconductor device having tungsten gates electrode Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a ... 11/23/06 - 20060263977 - Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to ... 11/23/06 - 20060263976 - Semiconductor device with capacitor structure for improving area utilization A semiconductor device with a capacitor structure for improving area utilization comprises a plurality of electrically conductive layers and a plurality of dielectric layers. The dielectric layers and the electrically conductive layers are alternately superposed one over another, and the electrically conductive layers are alternately electrically connected. ... 11/16/06 - 20060258088 - Capacitor arrangement in a semiconductor component and driving apparatus A semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has ... 10/19/06 - 20060234443 - Mim capacitor and method of fabricating same A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a ... 09/28/06 - 20060216886 - Sram devices having buried layer patterns and methods of forming the same An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed ... 09/21/06 - 20060211197 - Mos transistor and method of manufacturing the same In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that ... 09/14/06 - 20060205147 - Self-aligned buried contact pair A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls ... 09/14/06 - 20060205146 - Low resistance peripheral contacts while maintaining dram array integrity A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium ... 09/07/06 - 20060199332 - Method of forming storage node of capacitor in semiconductor memory, and structure therefor In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The ... 09/07/06 - 20060199331 - Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a polysilicon layer of a container ... 09/07/06 - 20060199330 - Method of manufacturing semiconductor memory having capacitor of high aspect ratio to prevent deterioration in insulating characteristics A method of manufacturing a semiconductor memory according to the present invention includes steps of forming an insulating film, into which a conductive plug connected to a source or a drain in a transistor in a memory cell region and into which a first conductive layer which will become a ... 09/07/06 - 20060199329 - Method for fabricating capacitor in semiconductor device A first insulation layer is formed on a substrate structure including an inter-layer insulation layer and a storage node contact plug. The first insulation layer is etched to form a first opening exposing a portion of the storage node contact plug. The first opening is filled with an organic polymer ... 08/24/06 - 20060189072 - Method and structure for metal-insulator-metal capacitor based memory device A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose ... 08/17/06 - 20060183281 - Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric ... 08/10/06 - 20060177981 - Capacitors and methods of manufacture thereof Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially ... 08/03/06 - 20060172489 - Method for producing a dielectric material on a semiconductor device and semiconductor device Method for producing a dielectric material on a semiconductor device with an atomic layer deposition procedure, whereby an aluminum oxide nitride or a silicon oxide nitride or an aluminum silicon oxide nitride layer is deposited comprising a rare earth metal-element. The invention describes a semiconductor device with a dielectric layer ... 07/27/06 - 20060166434 - Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first ... 07/20/06 - 20060160301 - Method for fabricating a metal-insulator-metal capacitor Disclosed are: (i) a method for fabricating a MIM capacitor in a semiconductor device, which can produce a MIM capacitor in fewer process steps; and (ii) a semiconductor device in which a MIM capacitor having a larger capacitance relative to conventional approaches is formed. The method comprises the steps of: ... 07/06/06 - 20060148170 - Fabricating method of semiconductor device A fabricating method of a semiconductor device includes: forming a first metal layer on a substrate and patterning the first metal layer to form a bottom metal line and a bottom electrode of a capacitor; forming an interlayer insulating layer on the resulting structure; forming a via hole in the ... 07/06/06 - 20060148169 - Mehods of fabricating mim capacitors Methods of fabricating MIM capacitors are provided. One example method includes forming an insulating layer including a void on a semiconductor substrate, forming a first hole connected to the void by patterning the insulating layer, forming a lower electrode by forming a tungsten layer filling in the first hole such ... 06/22/06 - 20060134861 - Semiconductor memory device and method for fabricating the same The present invention relates to a semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least more than two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer ... 06/22/06 - 20060134860 - Semiconductor processing methods Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation, a semiconductor wafer backside is mechanically scrubbed to remove an undesired material prior to forming a final passivation layer over an oppositely facing semiconductor wafer frontside. In another ... 06/22/06 - 20060134859 - Mask for forming landing plug contact hole and plug forming method using the same Disclosed herein are a mask for forming a landing plug contact hole to vertically expose an active region of a semiconductor substrate to a bit line or storage node contact, and a plug forming method using the same. Through the use of the crescent-shaped masks, it is possible to increase ... 06/15/06 - 20060128094 - Semiconductor integrated circuit device and method of manufacturing the same In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel ... 05/25/06 - 20060110878 - Side wall active pin memory and manufacturing method A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with ... 05/18/06 - 20060105521 - Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not ... 05/11/06 - 20060099761 - Dual-damascene process to fabricate thick wire structure A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch ... 05/04/06 - 20060094186 - Semiconductor device and method of manufacturing the same A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) ... 05/04/06 - 20060094185 - Capacitor including a dielectric layer having an inhomogeneous crystalline region and method of fabricating the same In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the ... 03/30/06 - 20060068544 - Semiconductor device with dram cell and method of manufacturing the same A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, isotropically forming a trench surface insulating film on an inner surface of the trench, the trench surface insulating film including a deep part functioning as a capacitor insulating film, forming a surface layer side insulating ... 03/09/06 - 20060051919 - Nanometric structure and corresponding manufacturing method A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between ... 03/09/06 - 20060051918 - Methods of forming a plurality of capacitors A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining ... 02/09/06 - 20060030101 - Semiconductor device and method for fabricating the same A method for fabricating a MIM capacitor with fewer process steps and decreased production cost. The method includes forming a via and a capacitor opening by selectively etching an insulating interlayer, wherein the via exposes the lower metal line and the capacitor opening is wider than the via, forming a ... 02/02/06 - 20060024884 - Semiconductor memory device and method of manufacturing the same A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned ... 02/02/06 - 20060024883 - Method for fabricating semiconductor memory device having cylinder type storage node Disclosed is a method for fabricating a semiconductor memory device capable of preventing a bunker defect caused by a pinhole or a crack on a single metal layer used as a storage node. The method includes the steps of: forming a plurality of storage node plugs on a substrate; forming ... 12/29/05 - 20050287738 - Method of manufacturing a semiconductor memory device A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a ... 12/15/05 - 20050277248 - Methods of forming void-free layers in openings of semiconductor substrates In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially ... 12/08/05 - 20050272203 - Modified source/drain re-oxidation method and system Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, ... 12/08/05 - 20050272202 - Random access memory A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and ... 11/17/05 - 20050255650 - Semiconductor device A semiconductor device includes an insulating film whose relative dielectric constant is 3.4 or less, at least one conductive layer, at least one conductive plug which is electrically connected to the conductive layer to form a conduction path, at least one reinforcing material whose Young's modulus is 30 GPa or ... 11/03/05 - 20050245027 - Method for fabricating a stacked capacitor array having a regular arrangement of a plurality of stacked capacitors The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain ... 11/03/05 - 20050245026 - Method of forming capacitor for semiconductor device A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and ... 10/27/05 - 20050239245 - Nonvolatile semiconductor memory and method of operating the same A nonvolatile semiconductor memory having a memory cell comprises: a semiconductor substrate having a pair of trenches formed on a surface thereof; first electrodes formed in a pair of trenches through the intervention of a first insulating film, respectively; a second electrode formed on the semiconductor substrate between the trenches ... 10/20/05 - 20050233520 - Semiconductor device and method for fabricating the same A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor ... 10/20/05 - 20050233519 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device. The method comprises steps of providing a substrate having a first metal layer and a second metal layer formed thereon. A first dielectric layer, an etching stop layer having a first opening located above the first metal layer and a second opening located ... 09/15/05 - 20050202630 - Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon ... 09/08/05 - 20050196920 - Semiconductor device with rare metal electrode A method of manufacturing a semiconductor device, includes the steps of: (a) forming a first inter-level insulating film on a semiconductor substrate formed with semiconductor elements; (b) forming a contact hole through the first inter-level insulating film; (c) forming a plug made of conductive material capable of being nitrided, the ... 08/25/05 - 20050186732 - Semiconductor devices having plug contact holes extending downward from a main surface of a semiconductor substrate and methods of forming the same According to some embodiments of the invention, semiconductor devices and DRAM cells have plug contact holes. Methods of forming the same include forming a channel-portion hole disposed in a semiconductor substrate. Lower portions of the plug contact holes between first and second word line patterns extend downward from the main ... 08/25/05 - 20050186731 - Atomic layer deposition method of forming an oxide comprising layer on a substrate This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed to form a first species monolayer onto the substrate within the deposition chamber from a gaseous first precursor. The chemisorbed ... 08/18/05 - 20050181561 - Nonvolatile semiconductor memory and manufacturing method thereof A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction ... 08/18/05 - 20050181560 - Storage capacitor having a scattering effect and method of manufacturing the same A storage capacitor having a scattering effect is positioned in a substrate for use in a thin film transistor array loop. The storage capacitor is characterized by having a rough layer overlapped by a medium layer and a passivation layer. The storage capacitor further has a reflective layer with high ... 08/18/05 - 20050181559 - Semiconductor device and method of manufacturing the same Disclosed is a method of manufacturing a semiconductor device, comprising forming a bottom electrode film of a capacitor above a semiconductor substrate, forming a dielectric film of the capacitor on the bottom electrode film, forming a top electrode film of the capacitor on the dielectric film, and forming a hydrogen ... 08/04/05 - 20050170585 - Methods for manufacturing semiconductor memory devices using sidewall spacers Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. Supporters also may be provided that are configured to support at ... 08/04/05 - 20050170584 - Compact and highly efficient dram cell A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a ... 08/04/05 - 20050170583 - Methods of fabricating mim capacitors of semiconductor devices Methods of fabricating a MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. A disclosed method comprises forming a first conducting material as a lower interconnect on a semiconductor substrate; sequentially depositing second and third insulating layers over the first conducting layer; performing a first damascene ... 07/28/05 - 20050164449 - Microelectronic capacitor structure and method for fabrication thereof Within a method for fabricating a capacitor structure within a microelectronic fabrication there is formed a capacitor structure comprising a pair of capacitor plate layers separated by a capacitor dielectric layer. Within the method, at least one of the pair of capacitor plates is formed of a doped amorphous silicon ... 07/28/05 - 20050164448 - Method for manufacturing a semiconductor device A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having ... 07/21/05 - 20050158949 - Semiconductor devices A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form ... 07/21/05 - 20050158948 - Semiconductor device having self-aligned contact plug and method for fabricating the same Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a ... 06/30/05 - 20050142737 - Methods of fabricating mim capacitors in semiconductor devices Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the first insulating layer; sequentially depositing a second insulating layer, a third ... 06/30/05 - 20050142736 - Methods of fabricating semiconductor devices Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the ... 06/30/05 - 20050142735 - Method of fabricating mos transistor A method of fabricating a CMOS (complementary metal oxide semiconductor) transistor includes manufacturing steps, by which adverse transistor characteristics can be prevented from being degraded by high-temperature annealing for hardening a screen oxide layer. The method includes steps of forming a gate on a semiconductor substrate with a gate oxide ... 06/30/05 - 20050142734 - Isolation methods in semiconductor devices Disclosed herein are isolation methods for use in semiconductor devices. One example method includes forming a hard mask layer by sequentially stacking a silicon oxide layer, a silicon nitride layer, and a thermal oxide layer on a semiconductor substrate, forming a hard mask layer pattern by patterning the hard mask ... 06/16/05 - 20050130371 - Method of fabricating semiconductor device having capacitor Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating ... 06/16/05 - 20050130370 - Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with ... 06/02/05 - 20050118762 - Manufacturing method of semiconductor device After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of ... ### FreshPatents.com Support |