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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Including Passive Device (e.g., Resistor, Capacitor, Etc.) > Capacitor > Trench Capacitor > Utilizing Stacked Capacitor Structure (e.g., Stacked Trench, Buried Stacked Capacitor, Etc.) Utilizing Stacked Capacitor Structure (e.g., Stacked Trench, Buried Stacked Capacitor, Etc.)Utilizing Stacked Capacitor Structure (e.g., Stacked Trench, Buried Stacked Capacitor, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082443 - Method for manufacturing liquid crystal display device A conventionally followed technique of manufacturing a liquid crystal display device is a method for forming various types of coatings over an entire surface of a substrate and for removing the coatings with a small region left by etching, which requires wasting a material cost and treating a large quantity ... 04/05/07 - 20070077703 - Semiconductor devices having improved gate insulating layers and related methods of fabricating such devices Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the ... 02/08/07 - 20070032014 - Methods of forming pluralities of capacitors The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the ... 01/18/07 - 20070015327 - Method of fabricating a trench capacitor dram device The present invention discloses a STI-first process for making trench DRAM devices. According to the preferred embodiment, the etching recipe for etching the STI region in the memory array is completely compatible with the logic STI process. ... 11/02/06 - 20060246658 - A capacitor electrode having an interface layer of different chemical composition formed on a bulk layer An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending ... 10/05/06 - 20060223261 - Cmos-based low esr capacitor and esd-protection device and method A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection. ... 09/14/06 - 20060205145 - Front-end processing of nickel plated bond pads A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. ... 06/01/06 - 20060115946 - Method of forming a lower electrode of a capacitor In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface ... 05/18/06 - 20060105520 - Structure and method to fabricate a protective sidewall liner for an optical mask Methods and structures for optical masks that have a liner on the trench sidewalls. An example embodiment comprises a mask structure for use with light at a wavelength comprising: a substrate having a first region, a second region and a third region; a first trench in the first region; a ... 04/20/06 - 20060084226 - Semiconductor memory device and method for fabricating the same A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side ... 10/27/05 - 20050239244 - Methods of forming storage nodes for a dram array The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the ... 10/13/05 - 20050227432 - Methods of forming metal-insulator-metal (mim) capacitors with separate seed and main dielectric layers and mim capacitors so formed A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of ... 09/29/05 - 20050215007 - Method and structure for enhancing trench capacitance A trench capacitor formed with a bottle etch step has a polygonal cross section produced by forming thermally oxidizing the trench walls with thinner oxide at the corners of the trench, then performing the bottle etch step with the nitride in place, thereby extending the trench walls laterally only outside ... 08/04/05 - 20050170582 - Semiconductor device and its manufacturing method A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first ... ### FreshPatents.com Support |