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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Including Passive Device (e.g., Resistor, Capacitor, Etc.) > Capacitor > Trench Capacitor Trench CapacitorTrench Capacitor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087501 - Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1 ... 04/19/07 - 20070087500 - Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer ... 04/19/07 - 20070087499 - Semiconductor memory device with vertical channel transistor and method of fabricating the same In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars ... 04/12/07 - 20070082442 - Recess gate transistor structure for use in semiconductor device and method thereof An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a ... 04/12/07 - 20070082441 - Trench fet with improved body to gate alignment A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through ... 04/12/07 - 20070082440 - Semiconductor device and manufacturing method thereof Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film ... 04/05/07 - 20070077702 - Trench memory cell and method for making the same A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric ... 03/29/07 - 20070072368 - Method of cleaning semiconductor surfaces Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is ... 03/29/07 - 20070072367 - Method of manufacturing semiconductor silicon substrate The present invention provides a method of manufacturing a semiconductor silicon substrate provided with a capacitor structure having a capacitor hole, the capacitor hole having a depth of equal to or greater than 3 μm and an aspect ratio equal to or greater than 30, the method including at least: ... 03/29/07 - 20070072366 - Transistor structure for semiconductor device and method of fabricating the same A transistor for a semiconductor device may include a lower semiconductor layer, an active pattern, including a groove region, on the lower semiconductor layer, a gate pattern at least partially overlapping the active pattern including the groove region, and a gate insulating layer interposed between the active pattern and the ... 03/29/07 - 20070072365 - Methods of forming a recessed gate A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on ... 03/22/07 - 20070066011 - Integrated circuitry production processes, methods, and systems The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a substrate. The organic material is contacted with a chemical mechanical polishing pad and a polishing fluid to remove the organic material from the substrate. The polishing fluid ... 03/22/07 - 20070066010 - Method of manufacturing semiconductor device The invention aims at enabling leakage current characteristics and a step coverage property to be improved by depositing a hafnium silicate film by utilizing an atomic layer evaporation method using a hafnium raw material, a silicon raw material and an oxidizing agent. Disclosed herein is a method of manufacturing a ... 03/01/07 - 20070048931 - Semiconductor device and its manufacture method (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting ... 03/01/07 - 20070048930 - Peripheral gate stacks and recessed array gates Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within ... 02/22/07 - 20070042542 - Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is ... 02/15/07 - 20070037347 - Capacitor of semiconductor device and method of fabricating the same A capacitor of a semiconductor device includes an oxide layer pattern including a trench formed on a semiconductor substrate, the trench having an inner wall and a bottom, quantum dots discontinuously formed on the inner wall of the trench, a bottom electrode formed on the inner wall and the bottom ... 02/15/07 - 20070037346 - Rapid thermal annealing of targeted thin film layers A method for rapid thermal annealing of thin film layers is provided. The method directs a series of pulses or flashes of heat energy toward a targeted layer on a substrate. Each pulse may be at a first temperature range sufficient to anneal the targeted layer, but has a duration ... 02/01/07 - 20070026602 - Method of minimal wafer support on bevel edge of wafer The present invention generally provides a method and apparatus for supporting and transferring a substrate in and out a wet cleaning chamber with minimal contact. One embodiment of the present invention provides an apparatus for support and transferring a substrate. The apparatus comprises a frame connected with an actuator configured ... 01/04/07 - 20070004130 - Fabrication method of a dynamic random access memory A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the ... 01/04/07 - 20070004129 - Semiconductor device having finfet and method of fabricating the same In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside ... 01/04/07 - 20070004128 - Method for fabricating semiconductor device with recess gate A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form ... 01/04/07 - 20070004127 - Method of fabricating a transistor having the round corner recess channel structure In fabricating a transistor having the round corner recess channel structure, a buffer layer and a hard mask layer are formed in the active area of a semiconductor substrate. The buffer layer and the hard mask layer are etched so as to expose a predetermined channel region of the active ... 01/04/07 - 20070004126 - Semiconductor device having a recess gate for improved reliability A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain ... 12/28/06 - 20060292789 - Structure and method for collar self-aligned to buried plate A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench. ... 12/14/06 - 20060281249 - Charge balance field effect transistor A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant ... 12/07/06 - 20060275978 - Deep trench formation in semiconductor device fabrication A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask ... 11/30/06 - 20060270151 - Method for forming a semiconductor device A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the ... 11/30/06 - 20060270150 - Method for forming a semiconductor device A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the ... 11/30/06 - 20060270149 - Method for forming a semiconductor device A method for forming a semiconductor device. A substrate, having a plurality of deep trench capacitors therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers on sidewalls of the upper portions of the deep trench capacitors are formed to form a predetermined region surrounded ... 11/02/06 - 20060246657 - Method of forming an insulation layer structure and method of manufacturing a semiconductor device using the same A method of forming an isolation layer structure for a semiconductor device includes forming a first structure on a substrate, the first structure including an insulation layer pattern having a sacrificial pattern therein, the sacrificial pattern having an etching rate that is different from the insulation layer pattern, partially removing ... 11/02/06 - 20060246656 - Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate on a single side via a buried contact for use in a semiconductor memory cell The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact, particularly for use in a semiconductor memory cell. More specifically, the present invention relates to a manufacturing method for ... 10/26/06 - 20060240614 - Field effect transistor A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor ... 10/19/06 - 20060234441 - Method for preparing a deep trench A method for preparing a deep trench first forms a trench in a semiconductor substrate and a stacked structure in the trench, wherein the stacked structure includes at least one nitrogen-containing layer. A phosphorous oxide layer is then formed on the surface of the nitrogen-containing layer. The phosphorous oxide is ... 10/19/06 - 20060234440 - Alignment mark and alignment method for the fabrication of trench-capacitor dram devices A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench ... 10/12/06 - 20060228856 - Method of fabricating semiconductor device A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and ... 10/05/06 - 20060223260 - Trench mosfet with sidewall spacer gates A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface ... 09/28/06 - 20060216885 - Method for fabricating semiconductor device Disclosed herein is a method for fabricating a memory device. According to the present invention, during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate ... 09/21/06 - 20060211196 - Semiconductor memory device and manufacturing method thereof A semiconductor memory device includes: a semiconductor substrate; a plurality of trench capacitors each including a capacitor dielectric film formed on a sidewall of a first trench to be formed in the semiconductor substrate, a storage node formed so as to bury the first trench via the capacitor dielectric film, ... 09/14/06 - 20060205144 - Trench capacitor and method for preparing the same The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom electrode, a top electrode positioned on the dielectric ... 08/31/06 - 20060194385 - Method of fabricating flash memory device A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barrier oxide films on lateral faces of the ... 08/24/06 - 20060189071 - Integrated circuit capacitor and method of manufacturing same A method for fabricating a capacitor using supercritical CO2 deposition of metal film layers in a reducing environment from precursors, such as metallo-organic precursors is provided. The method can generate conformal growth on a 3-D cell structure at a relatively high speed, while minimizing the occurrence of oxidation of precursors ... 08/24/06 - 20060189070 - Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first ... 08/24/06 - 20060189069 - Structure and method for integrating mim capacitor in beol wiring levels A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating ... 08/10/06 - 20060177980 - Capacitorless 1-transistor dram cell and fabrication method A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical ... 08/10/06 - 20060177979 - Method of manufacturing a capacitor and a metal gate on a semiconductor device A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor ... 07/27/06 - 20060166433 - Recessed collar etch for buried strap window formation without poly2 A method for manufacturing a trench capacitor with a reduced resistance in a buried strap window for use in a memory circuit such as a dynamic random access memory circuit may be realized by reducing the number of polysilicon layers that are deposited. The method includes the deposition of a ... 07/20/06 - 20060160298 - Self-aligned, silicided, trench-based, dram/edram processes with improved retention A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond ... 06/29/06 - 20060141701 - Semiconductor device having trench capacitors and method for making the trench capacitors A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film ... 06/29/06 - 20060141700 - Method for fabricating semiconductor memory device having recessed storage node contact plug A semiconductor memory device and a method for fabricating a semiconductor memory device are provided. The method includes forming an inter-layer insulation layer having a storage node contact hole on a substrate; forming a pair of storage node contact spacers on sidewalls of the storage node contact hole; forming a ... 06/29/06 - 20060141699 - Method for fabricating semiconductor memory device A method for fabricating a semiconductor memory device is provided. The method includes: forming an inter-layer insulation layer with a storage node contact hole on a substrate; forming storage node contact spacers on sidewalls of the inter-layer insulation layer in the storage node contact hole; forming a storage node contact ... 06/22/06 - 20060134858 - Method of manufacturing semiconductor device A silicon nitride film is formed on a P-type silicon substrate; an opening of a predetermined pattern is formed in the silicon nitride film; a gate trench is formed on the semiconductor substrate using a silicon nitride film as a mask; and then a polycrystalline silicon film is embedded inside ... 06/22/06 - 20060134857 - Memory device and fabrication thereof A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface ... 06/15/06 - 20060128093 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is provided. The method comprises forming a mask member on a surface of a semiconductor substrate; and forming a trench in the semiconductor substrate by selectively etching the semiconductor substrate with a mask of the mask member under a certain pressure. The pressure ... 06/08/06 - 20060121672 - Methods of forming pluralities of capacitors, and integrated circuitry A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is ... 05/04/06 - 20060094184 - Semiconductor storage device and method for manufacturing the same There is disclosed a semiconductor storage device comprising a trench capacitor wherein a high dielectric-constant insulator is used and formation of a depletion layer in a capacitor electrode is suppressed. The semiconductor storage device comprises a trench formed in a semiconductor substrate, a high dielectric-constant insulator formed on an inner ... 04/20/06 - 20060084225 - Apparatus for forming dielectric structures in integrated circuits In some embodiments, a multi-layer dielectric structure, such as a capacitor dielectric region, is formed by forming a first dielectric layer on a substrate according to a CVD process and forming a second dielectric layer directly on the first dielectric layer according to an ALD process. In further embodiments, a ... 04/20/06 - 20060084224 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor devise comprising: a gate electrode formed via a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a source region and drain region formed in a surface portion of said semiconductor substrate on two sides of ... 04/20/06 - 20060084223 - Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate ... 04/20/06 - 20060084222 - Process for fabricating a semiconductor device having deep trench structures A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer ... 04/13/06 - 20060079049 - Method for fabricating a capacitor In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is ... 03/30/06 - 20060068543 - Electro-and electroless plating of metal in the manufacture of pcram devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a ... 03/23/06 - 20060063326 - Chemical mechanical polishing method A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) ... 03/09/06 - 20060051916 - Deep trench capacitor and method of fabricating thereof A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. ... 02/16/06 - 20060035430 - Fabrication method for a trench capacitor having an insulation collar The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side ... 01/26/06 - 20060019443 - Top-oxide-early process and array top oxide planarization Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of ... 01/19/06 - 20060014344 - Methods of forming semiconductor structures and capacitor devices The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the ... 01/05/06 - 20060003525 - Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further ... 01/05/06 - 20060003524 - Method for forming trench memory cell structures for drams One embodiment of the invention relates to a method for forming trench memory cell structures having trench capacitors and planar selection transistors. An implantation for forming a reinforcement implant for improving the electrical connection of a storage electrode of a trench capacitor to a first source/drain zone of the respective ... 12/15/05 - 20050277247 - Method for fabricating a trench capacitor of dram This invention discloses a method for fabricating a deep trench capacitor. A substrate is provided. A pad oxide layer and a pad nitride layer are stacked on a main surface of the substrate. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride ... 12/08/05 - 20050272201 - Improved process for forming a buried plate A method of making a buried plate region in a semiconductor substrate is provided. A trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A liner is formed along at least ... 11/24/05 - 20050260812 - Memory cell having a trench capacitor and method for fabricating a memory cell and trench capacitor A memory cell having a trench capacitor, a trench capacitor, and a method is disclosed. In one embodiment, the method for fabricating a trench capacitor with a first capacitor electrode, a first capacitor dielectric, a second capacitor electrode, a second capacitor dielectric and third capacitor electrode, includes connecting the first ... 11/03/05 - 20050245025 - Method of fabricating bottle trench capacitors using an electrochemical etch with electrochemical etch stop A method of forming trench capacitors in, e. g., a DRAM device, using an electrochemical etch with built-in etch stop to fabricate well-defined bottle-shaped capacitors is described. The process includes formation of a sacrificial silicon layer after initial deep trench formation, wherein the sacrificial layer is formed by doping, and ... 11/03/05 - 20050245024 - Method for production of trench dram cells and a trench dram cell array with fin field-effect transistors with a curved channel (cfet - curved fets) A method for producing trench DRAM cells, each having a trench capacitor and a fin field-effect transistor with a curved channel (CFET) for addressing the trench capacitor, is described. The memory cells are arranged in cell rows offset with respect to one another and are separated from one another by ... 10/06/05 - 20050221557 - Method for producing a deep trench capacitor in a semiconductor substrate The present invention provides a method for producing a deep trench capacitor in a semiconductor substrate (1) comprising the steps of: providing a first trench (2) in the semiconductor substrate (1); oxidizing the semiconductor substrate (1) in the first trench (2) for providing an oxidized silicon layer (3); depositing a ... 09/15/05 - 20050202628 - Dynamic random access memory cell and method for fabricating the same A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of ... 09/08/05 - 20050196919 - Top oxide nitride liner integration scheme for vertical dram A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas ... 09/08/05 - 20050196918 - Dram memory and method for fabricating a dram memory cell A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench capacitor. The memory cells are arranged in cell rows which are offset with respect to one another and are separated from one another by trench insulator ... 09/01/05 - 20050191806 - Method for fabricating a memory cell The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a trench-like recess (102) etched into the substrate (101), conductive material, which is provided as a projection in a central region of the trench-like recess (102) ... 09/01/05 - 20050191805 - Semiconductor fabrication using a collar In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first memory container of the number of memory containers is in contact with the collar material along a side of a second memory container. An ... 08/25/05 - 20050186730 - Trench device structure with single-side buried strap and method for fabricating the same A trench device with collar oxide for isolation. A buried trench capacitor is formed in a lower portion of a deep trench in a substrate. A conductive layer, surrounded by a collar insulating layer and lower than the collar insulating layer, is deposited in an upper portion of the trench. ... 08/11/05 - 20050176198 - Method of fabricating bottle trench capacitors using an electrochemical etch with electrochemical etch stop A method of forming trench capacitors in, e.g., a DRAM device, using an electrochemical etch with built-in etch stop to fabricate well-defined bottle-shaped capacitors is described. The process includes formation of a sacrificial silicon layer after initial deep trench formation, wherein the sacrificial layer is formed by doping, and upon ... 08/11/05 - 20050176197 - Line mask defined active areas for 8f2 dram cells with folded bit lines and deep trench patterns A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and ... 08/04/05 - 20050170581 - Method for forming bottle shaped trench Disclosed is a method for forming a bottle shaped trench. The method of the present invention includes steps of providing a substrate; forming a plurality of operation layers on the substrate; forming a photoresist layer on the operation layers to define a predetermined position; forming a trench according to the ... 07/28/05 - 20050164446 - Method for manufacturing single-sided buried strap in semiconductor devices A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess ... 07/21/05 - 20050158946 - Methods of forming spaced conductive regions, methods of recessing conductive material and methods of forming capacitor constructions The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a semiconductor substrate. The construction also includes openings extending through the first electrically conductive material and into the semiconductor substrate. A second electrically conductive material is formed within ... 07/21/05 - 20050158945 - Memory cell and method for fabricating it The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression ... 07/14/05 - 20050153507 - Fabrication method for a trench capacitor with an insulation collar The present invention provides a fabrication method for a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact. After forming and sinking an electrically conductive filling, an insulation collar and, if appropriate, a buried contact that ... 07/14/05 - 20050153506 - Isolation structure for trench capacitors and fabrication method thereof This invention relates to a method for self-aligned fabricating an isolation structure of a trench capacitor. The method takes two steps to etch the substrate for forming the shallow trench of the isolation structure, wherein the conductive layer and the collar oxide layer of the trench capacitor remain intact during ... 07/07/05 - 20050148140 - Method for scalable, low-cost polysilicon capacitor in a planar dram Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor ... 06/30/05 - 20050142732 - Semiconductor device and fabricating method thereof The present invention provides a semiconductor device and fabricating method thereof, by which capacitance is enhanced by increasing an effective area of a lower electrode of a capacitor. The present invention includes a first lower electrode on a semiconductor substrate to have a plate shape, a second lower electrode on ... 06/23/05 - 20050136590 - Method for forming capacitor of semiconductor device Disclosed is a method for forming a capacitor of a semiconductor device. The method comprises the steps of: forming a nitride film for storage electrode on a semiconductor substrate; forming an oxide film for storage electrode on the nitride film; selectively etching the oxide film and the nitride film to ... ### FreshPatents.com Support |