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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Including Passive Device (e.g., Resistor, Capacitor, Etc.) > Capacitor > And Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) And Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.)And Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087498 - Methods of forming buried bit line dram circuitry A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within ... 01/12/06 - 20060008979 - Methods of forming buried bit line dram circuitry A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within ... 12/01/05 - 20050266636 - Semiconductor device and method of manufacturing the same In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper ... 08/25/05 - 20050186729 - Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the ... 08/25/05 - 20050186728 - Semiconductor memory device and method for manufacturing the same A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a ... 06/09/05 - 20050124111 - Method for forming a self-aligned buried strap in a vertical memory cell A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the ... 06/09/05 - 20050124110 - Method for forming a self-aligned buried strap in a vertical memory cell A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act ... ### FreshPatents.com Support |